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? 2004 microchip technology inc. preliminary ds39635a pic18f6310/6410/8310/8410 data sheet 64/80-pin flash microcontrollers with nanowatt technology
ds39635a-page ii preliminary ? 2004 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of mi crochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance ar e trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2004 microchip technology inc. preliminary ds39635a-page 1 pic18f6310/6410/8310/8410 power managed modes: run: cpu on, peripherals on idle: cpu off, peripherals on sleep: cpu off, peripherals off idle mode currents down to 5.8 a typical sleep mode currents down to 0.1 a typical timer1 oscillator: 1.8 a, 32 khz, 2v watchdog timer: 2.1 a two-speed oscillator start-up flexible oscillator structure: four crystal modes: - lp: up to 200 khz - xt: up to 4 mhz - hs: up to 40 mhz - hspll: 4-10 mhz (16-40 mhz internal) 4x phase lock loop (available for crystal and internal oscillators) two external rc modes, up to 4 mhz two external clock modes, up to 40 mhz internal oscillator block: - 8 user selectable frequencies, from 31 khz to 8 mhz - provides a complete range of clock speeds from 31 khz to 32 mhz when used with pll - user-tunable to compensate for frequency drift secondary oscillator using timer1 @ 32 khz fail-safe clock monitor: - allows for safe shut down of device if primary or secondary clock fails external memory interface (pic18f8310/8410 devices only): address capability of up to 2 mbytes 16-bit/8-bit interface peripheral highlights: high current sink/source 25 ma/25 ma four external interrupts four input change interrupts four 8-bit/16-bit timer/counter modules up to 3 capture/compare/pwm (ccp) modules master synchronous serial port (mssp) module supporting 3-wire spi? (all 4 modes) and i 2 c? master and slave modes addressable usart module: - supports rs-485 and rs-232 enhanced addressable usart module: - supports rs-485, rs-232 and lin 1.2 - auto-wake-up on start bit - auto-baud detect 10-bit, up to 12-channel analog-to-digital converter module (a/d): - auto-acquisition capability - conversion available during sleep dual analog comparators with input multiplexing special microcontroller features: c compiler optimized architecture: - optional extended instruction set designed to optimize re-entrant code 1000 erase/write cycle flash program memory typical flash retention: 100 years typical priority levels for interrupts 8 x 8 single-cycle hardware multiplier extended watchdog timer (wdt): - programmable period from 4 ms to 131s - 2% stability over v dd and temperature in-circuit serial programming? (icsp?) via two pins in-circuit debug (icd) via two pins wide operating voltage range: 2.0v to 5.5v device program memory (on-board/external) data memory i/o 10-bit a/d (ch) ccp (pwm) mssp eusart/ ausart comparators timers 8/16-bit ext. bus flash (bytes) # single-word instructions sram (bytes) spi? master i 2 c? pic18f6310 8k/0 4096/0 768 54 12 3 y y 1/1 2 1/3 n pic18f6410 16k/0 8192/0 768 54 12 3 y y 1/1 2 1/3 n pic18f8310 8k/2m 4096/1m 768 70 12 3 y y 1/1 2 1/3 y pic18f8410 16k/2m 8192/1m 768 70 12 3 y y 1/1 2 1/3 y 64/80-pin flash microcontrollers with nanowatt technology
pic18f6310/6410/8310/8410 ds39635a-page 2 preliminary ? 2004 microchip technology inc. pin diagrams 64-pin tqfp pic18f6310 1 2 3 4 5 6 7 8 9 10 11 12 13 14 38 37 36 35 34 33 50 49 17 18 19 20 21 22 23 24 25 26 re2/cs re3 re4 re5 re6 re7/ccp2 (1) rd0/psp0 v dd v ss rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 re1/wr re0/rd rg0/ccp3 rg1/tx2/ck2 rg2/rx2/dt2 rg3 rg5/mclr /v pp rg4 v ss v dd rf7/ss rf6/an11 rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rb0/int0 rb1/int1 rb2/int2 rb3/int3 rb4/kbi0 rb5/kbi1 rb6/kbi2/pgc v ss osc2/clko/ra6 osc1/clki/ra7 v dd rb7/kbi3/pgd rc4/sdi/sda rc3/sck/scl rc2/ccp1 rf0/an5 rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/an4/hlvdin rc1/t1osi/ccp2 (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 rc5/sdo 15 16 31 40 39 27 28 29 30 32 48 47 46 45 44 43 42 41 54 53 52 51 58 57 56 55 60 59 64 63 62 61 note 1: re7 is the alternate pin for ccp2 multiplexing . pic18f6410
? 2004 microchip technology inc. preliminary ds39635a-page 3 pic18f6310/6410/8310/8410 pin diagrams (continued ) 80-pin tqfp note 1: re7 is the alternate pin for ccp2 multiplexing . pic18f8310 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 re2/ad10/cs re3/ad11 re4/ad12 re5/ad13 re6/ad14 re7/ccp2 (1) /ad15 rd0/ad0/psp0 v dd v ss rd1/ad1/psp1 rd2/ad2/psp2 rd3/ad3/psp3 rd4/ad4/psp4 rd5/ad5/psp5 rd6/ad6/psp6 rd7/ad7/psp7 re1/ad9/wr re0/ad8/rd rg0/ccp3 rg1/tx2/ck2 rg2/rx2/dt2 rg3 rg5/mclr /v pp rg4 v ss v dd rf7/ss rb0/int0 rb1/int1 rb2/int2 rb3/int3/ccp2 (1) rb4/kbi0 rb5/kbi1 rb6/kbi2/pgc v ss osc2/clko/ra6 osc1/clki/ra7 v dd rb7/kbi3/pgd rc4/sdi/sda rc3/sck/scl rc2/ccp1 rf0/an5 rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/an4/hlvdin rc1/t1osi/ccp2 (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 rc5/sdo rj0/ale rj1/oe rh1/a17 rh0/a16 1 2 rh2/a18 rh3/a19 17 18 rh7 rh6 rh5 rh4 rj5/ce rj4/ba0 37 rj7/ub rj6/lb 50 49 rj2/wrl rj3/wrh 19 20 33 34 35 36 38 58 57 56 55 54 53 52 51 60 59 68 67 66 65 72 71 70 69 74 73 78 77 76 75 79 80 rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rf6/an11 pic18f8410
pic18f6310/6410/8310/8410 ds39635a-page 4 preliminary ? 2004 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 oscillator configurations ................................................................................................... ......................................................... 29 3.0 power managed modes ......................................................................................................... .................................................... 39 4.0 reset ....................................................................................................................... ................................................................... 49 5.0 memory organization ......................................................................................................... ........................................................ 61 6.0 program memory.............................................................................................................. .......................................................... 85 7.0 external memory interface ................................................................................................... ...................................................... 89 8.0 8 x 8 hardware multiplier................................................................................................... ......................................................... 99 9.0 interrupts .................................................................................................................. ................................................................ 101 10.0 i/o ports .................................................................................................................. ................................................................. 117 11.0 timer0 module .............................................................................................................. ........................................................... 143 12.0 timer1 module .............................................................................................................. ........................................................... 147 13.0 timer2 module .............................................................................................................. ........................................................... 153 14.0 timer3 module .............................................................................................................. ........................................................... 155 15.0 capture/compare/pwm (ccp) modules .......................................................................................... ....................................... 159 16.0 master synchronous serial port (mssp) module ............................................................................... ..................................... 169 17.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) .................................................. ............. 209 18.0 addressable universal synchronous asynchr onous receiver transmitter (ausart) ............................................... ............ 231 19.0 10-bit analog-to-digital converter (a/d) module ............................................................................ ......................................... 245 20.0 comparator module.......................................................................................................... ........................................................ 255 21.0 comparator voltage reference module ........................................................................................ ........................................... 261 22.0 high/low-voltage detect (hlvd)............................................................................................. ................................................ 265 23.0 special features of the cpu ................................................................................................ .................................................... 271 24.0 instruction set summary .................................................................................................... ...................................................... 287 25.0 development support........................................................................................................ ....................................................... 337 26.0 electrical characteristics ................................................................................................. ......................................................... 343 27.0 dc and ac characteristics graphs and tables ................................................................................ ....................................... 379 28.0 packaging information...................................................................................................... ........................................................ 381 appendix a: revision history................................................................................................... .......................................................... 385 appendix b: device differences................................................................................................. ........................................................ 385 appendix c: conversion considerations .......................................................................................... ................................................. 386 appendix d: migration from baseline to enhanced devices........................................................................ ...................................... 386 appendix e: migration from mid-range to enhanced devices ....................................................................... ................................... 387 appendix f: migration from high-end to enhanced devices ........................................................................ ..................................... 387 index .......................................................................................................................... ........................................................................ 389 on-line support................................................................................................................ ................................................................. 399 systems information and upgrade hot line ....................................................................................... ............................................... 399 reader response ................................................................................................................ .............................................................. 400 pic18f6310/6410/8310/8410 product identification system ........................................................................ .................................... 401
? 2004 microchip technology inc. preliminary ds39635a-page 5 pic18f6310/6410/8310/8410 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/doc umentation issues become known to us, we will publis h an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: microchip?s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) the microchip corporate literatu re center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de literature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
pic18f6310/6410/8310/8410 ds39635a-page 6 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 7 pic18f6310/6410/8310/8410 1.0 device overview this document contains device specific information for the following devices: this family offers the advantages of all pic18 microcontrollers ? namely, high computational performance at an economical price. in addition to these features, the pic18f6310/6410/8310/8410 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. 1.1 new core features 1.1.1 nanowatt technology all of the devices in the pic18f6310/6410/8310/8410 family incorporate a range of features that can significantly reduce power consumption during operation. key items include: alternate run modes: by clocking the controller from the timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. multiple idle modes: the controller can also run with its cpu core disabled, but the peripherals still active. in these states, power consumption can be reduced even further ? to as little as 4% of normal operation requirements. on-the-fly mode switching: the power managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application?s software design. lower consumption in key modules: the power requirements for both timer1 and the watchdog timer have been reduced by up to 80%, with typical values of 1.1 a and 2.1 a, respectively. 1.1.2 multiple oscillator options and features all of the devices in the pic18f6310/6410/8310/8410 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. these include: four crystal modes, using crystals or ceramic resonators. two external clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general i/o). two external rc oscillator modes, with the same pin options as the external clock modes. an internal oscillator block which provides an 8 mhz clock (2% accuracy) and an intrc source (approximately 31 khz, stable over temperature and v dd ), as well as a range of six user selectable clock frequencies between 125 khz to 4 mhz for a total of eight clock frequencies. this option frees the two oscillator pins for use as additional general purpose i/o. a phase lock loop (pll) frequency multiplier, available to both the high-speed crystal and internal oscillator modes, which allows clock speeds of up to 40 mhz. used with the internal oscillator, the pll gives users a complete selection of clock speeds from 31 khz to 32 mhz ? all without using an external crystal or clock circuit. besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: fail-safe clock monitor: this option constantly monitors the main clock source against a reference signal provided by the internal oscillator. if a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown. two-speed start-up: this option allows the internal oscillator to serve as the clock source from power-on reset or wake-up from sleep mode until the primary clock source is available. pic18f6310 pic18lf6310 pic18f6410 pic18lf6410 pic18f8310 PIC18LF8310 pic18f8410 pic18lf8410
pic18f6310/6410/8310/8410 ds39635a-page 8 preliminary ? 2004 microchip technology inc. 1.2 other special features memory endurance: the flash cells for program memory are rated to last for approximately a thousand erase/write cycles. data retention without refresh is conservatively estimated to be greater than 100 years. external memory interface: for those applications where more program or data storage is needed, the pic18f8310/8410 devices provide the ability to access external memory devices. the memory interface is configurable for both 8-bit and 16-bit data widths and uses a standard range of control signals to enable communication with a wide range of memory devices. with their 21-bit program counters, the 80-pin devices can access a linear memory space of up to 2 mbytes. extended instruction set: the pic18f6310/6410/8310/8410 family introduces an optional extension to the pic18 instruction set, which adds 8 new instructions and an indexed addressing mode. this extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages such as ?c?. enhanced addressable usart: this serial communication module is capable of standard rs-232 operation and provides support for the lin bus protocol. other enhancements include automatic baud rate detection and a 16-bit baud rate generator for improved resolution. when the microcontroller is using the internal oscillator block, the eusart provides stable operation for applications that talk to the outside world, without using an external crystal (or its accompanying power requirement). 10-bit a/d converter: this module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduces code overhead. extended watchdog timer (wdt): this enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over 2 minutes that is stable across operating voltage and temperature. 1.3 details on individual family members devices in the pic18f6310/6410/8310/8410 family are available in 64-pin (pic18f6310/8310) and 80-pin (pic18f6410/8410) packages. block diagrams for the two groups are shown in figure 1-1 and figure 1-2, respectively. the devices are differentiated from each other in three ways: 1. flash program memory: 8 kbytes in pic18fx310 devices, 16 kbytes in pic18fx410 devices. 2. i/o ports: 7 bidirectional ports on 64-pin devices, 9 bidirectional ports on 80-pin devices. 3. external memory interface: present on 80-pin devices only. all other features for devices in this family are identical. these are summarized in table 1-1. the pinouts for all devices are listed in table 1-2 and table 1-3. like all microchip pic18 devices, members of the pic18f6310/6410/8310/8410 family are available as both standard and low-voltage devices. standard devices with flash memory, designated with an ?f? in the part number (such as pic18f6310), accommodate an operating v dd range of 4.2v to 5.5v. low-voltage parts, designated by ?lf? (such as pic18lf6410), function over an extended v dd range of 2.0v to 5.5v.
? 2004 microchip technology inc. preliminary ds39635a-page 9 pic18f6310/6410/8310/8410 table 1-1: device features features pic18f6310 pic18f6410 pic18f8310 pic18f8410 operating frequency dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz program memory (bytes) 8k 16k 8k 16k program memory (instructions) 4096 8192 4096 8192 data memory (bytes) 768 768 768 768 external memory interface no no yes yes interrupt sources 22 22 22 22 i/o ports ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g, h, j ports a, b, c, d, e, f, g, h, j timers 4444 capture/compare/pwm modules 3 3 3 3 serial communications mssp, ausart enhanced usart mssp, ausart enhanced usart mssp, ausart enhanced usart mssp, ausart enhanced usart parallel communications psp psp psp psp 10-bit analog-to-digital module 12 input channels 12 input channels 12 input channels 12 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt programmable low-voltage detect yes yes yes yes programmable brown-out reset yes yes yes yes instruction set 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled packages 64-pin tqfp 64-pin tqfp 80-pin tqfp 80-pin tqfp
pic18f6310/6410/8310/8410 ds39635a-page 10 preliminary ? 2004 microchip technology inc. figure 1-1: pic18f6310/6410 (64-pin) block diagram instruction decode and control porta portb portc ra4/t0cki ra5/an4/hlvdin rb0/int0 rc0/t1oso/t13cki rc1/t1osi/ccp2 (1) rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx1/ck1 rc7/rx1/dt1 ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 rb1/int1 data latch data memory (8/16 kbytes) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> address latch program memory (48/64 kbytes) data latch 20 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 rb2/int2 rb3/int3 pclatu pcu portd rd7/psp7:rd0/psp0 osc2/clko (3) /ra6 note 1: ccp2 is multiplexed with rc1 when configuration bit ccp2mx is set, or re7 when ccp2mx is not set. 2: rg5 is only available when mclr functionality is disabled. 3: osc1/clki and osc2/clko are only available in select oscillator modes and when these pins are not being used as digital i/o. refer to section 2.0 ?oscillator configurations? for additional information. rb4/kbi0 rb5/kbi1 rb6/kbi2/pgc rb7/kbi3/pgd eusart1 comparators mssp timer2 timer1 timer3 timer0 hlvd ccp1 bor adc 10-bit w instruction bus <16> stkptr bank 8 state machine control signals decode 8 8 power-up timer oscillator start-up timer power-on reset watchdog timer osc1 (3) osc2 (3) v dd , brown-out reset internal oscillator fail-safe clock monitor precision reference band gap v ss mclr (2) block intrc oscillator 8 mhz oscillator single-supply programming in-circuit debugger t1osi t1oso osc1/clki (3) /ra7 porte re0/rd re1/wr re2/cs re3 re4 re5 re6 re7/ccp2 (1) portf rf0/an5 rf1/an6/c2out rf2/an7/c1out rf3/an8 rf4/an 9 rf5/an10/cv ref rf6/an11 rf7/ss portg rg0 /ccp3 rg1/tx2/ck2 rg2/rx2/dt2 rg3 rg4 rg5 (2) /mclr /v pp ausart2 ccp2 rom latch ccp3
? 2004 microchip technology inc. preliminary ds39635a-page 11 pic18f6310/6410/8310/8410 figure 1-2: pic18f8310/8410 (80-pin) block diagram prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> 8 8 3 note 1: ccp2 multiplexing is determined by the settings of the ccp2mx and pm1:pm0 configuration bits. 2: rg5 is only available when mclr functionality is disabled. 3: osc1/clki and osc2/clko are only available in select oscillator modes and when these pins are not being used as digital i/o. refer to section 2.0 ?oscillator configurations? for additional information. w 8 8 8 power-up timer oscillator start-up timer power-on reset watchdog timer osc1 (3) osc2 (3) v dd , brown-out reset internal oscillator fail-safe clock monitor precision reference band gap v ss mclr (2) block intrc oscillator 8 mhz oscillator single-supply programming in-circuit debugger t1osi t1oso porth rh7:rh4 rh3/ad19:rh0/ad16 porta portb portc ra4/t0cki ra5/an4/hlvdin rb0/int0 rc0/t1oso/t13cki rc1/t1osi/ccp2 (1) rc2/ccp1 rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx1/ck1 rc7/rx1/dt1 ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 rb1/int1 rb2/int2 rb3/int3/ccp2 (1) portd osc2/clko (3) /ra6 rb4/kbi0 rb5/kbi1 rb6/kbi2/pgc rb7/kbi3/pgd osc1/clki (3) /ra7 porte portf rf0/an5 rf1/an6/c2out rf2/an7/c1out rf3/an8 rf4/an9 rf5/an10/cv ref rf6/an11 rf7/ss portg rg0/ccp3 rg1/tx2/ck2 rg2/rx2/dt2 rg3 rg4 rg5 (2) /mclr /v pp eusart1 comparators mssp timer2 timer1 timer3 timer0 hlvd ccp1 bor adc 10-bit ausart2 ccp2 ccp3 instruction decode & control data latch data memory (8/16 kbytes) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4124 pch pcl pclath 8 31 level stack program counter address latch program memory (48/64 kbytes) data latch 20 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 rom latch pclatu pcu instruction bus <16> stkptr bank state machine control signals decode system bus interface ad15:ad0, a19:a16 rd7/ad7/psp7: rd0/ad0/psp0 re0/ad8/rd re1/ad9/wr re2/ad10/cs re3/ad11 re4/ad12 re5/ad13 re6/ad14 re7/ccp2 (1) /ad15 portj rj0/ale rj1/oe rj2/wrl rj3/wrh rj4/ba0 rj5/ce rj6/lb rj7/ub (multiplexed with portd, porte and porth)
pic18f6310/6410/8310/8410 ds39635a-page 12 preliminary ? 2004 microchip technology inc. table 1-2: pic18f6310/6410 pinout i/o descriptions pin name pin number pin type buffer type description tqfp rg5/mclr /v pp rg5 mclr v pp 7 i i p st st master clear (input) or programming voltage (input). digital input. master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. osc1/clki/ra7 osc1 clki ra7 39 i i i/o st cmos ttl oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode, cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 40 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit ccp2mx is set. 2: alternate assignment for ccp2 when configuration bit ccp2mx is cleared.
? 2004 microchip technology inc. preliminary ds39635a-page 13 pic18f6310/6410/8310/8410 porta is a bidirectional i/o port. ra0/an0 ra0 an0 24 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 23 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 22 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 21 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 28 i/o i st/od st digital i/o. open-drain when configured as output. timer0 external clock input. ra5/an4/hlvdin ra5 an4 hlvdin 27 i/o i i ttl analog analog digital i/o. analog input 4. high/low-voltage detect input. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. table 1-2: pic18f6310/6410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit ccp2mx is set. 2: alternate assignment for ccp2 when configuration bit ccp2mx is cleared.
pic18f6310/6410/8310/8410 ds39635a-page 14 preliminary ? 2004 microchip technology inc. portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0 rb0 int0 48 i/o i ttl st digital i/o. external interrupt 0. rb1/int1 rb1 int1 47 i/o i ttl st digital i/o. external interrupt 1. rb2/int2 rb2 int2 46 i/o i ttl st digital i/o. external interrupt 2. rb3/int3 rb3 int3 45 i/o i ttl st digital i/o. external interrupt 3. rb4/kbi0 rb4 kbi0 44 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb5/kbi1 rb5 kbi1 43 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb6/kbi2/pgc rb6 kbi2 pgc 42 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 37 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-2: pic18f6310/6410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit ccp2mx is set. 2: alternate assignment for ccp2 when configuration bit ccp2mx is cleared.
? 2004 microchip technology inc. preliminary ds39635a-page 15 pic18f6310/6410/8310/8410 portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 30 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 (1) 29 i/o i i/o st cmos st digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm 2 output. rc2/ccp1 rc2 ccp1 33 i/o i/o st st digital i/o. capture 1 input/compare 1 output/pwm 1 output. rc3/sck/scl rc3 sck scl 34 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi? mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi/sda rc4 sdi sda 35 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 36 i/o o st ? digital i/o. spi data out. rc6/tx1/ck1 rc6 tx1 ck1 31 i/o o i/o st ? st digital i/o. eusart1 asynchronous transmit. eusart1 synchronous clock (see related rx1/dt1). rc7/rx1/dt1 rc7 rx1 dt1 32 i/o i i/o st st st digital i/o. eusart1 asynchronous receive. eusart1 synchronous data (see related tx1/ck1). table 1-2: pic18f6310/6410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit ccp2mx is set. 2: alternate assignment for ccp2 when configuration bit ccp2mx is cleared.
pic18f6310/6410/8310/8410 ds39635a-page 16 preliminary ? 2004 microchip technology inc. portd is a bidirectional i/o port. rd0/psp0 rd0 psp0 58 i/o i/o st ttl digital i/o. parallel slave port data. rd1/psp1 rd1 psp1 55 i/o i/o st ttl digital i/o. parallel slave port data. rd2/psp2 rd2 psp2 54 i/o i/o st ttl digital i/o. parallel slave port data. rd3/psp3 rd3 psp3 53 i/o i/o st ttl digital i/o. parallel slave port data. rd4/psp4 rd4 psp4 52 i/o i/o st ttl digital i/o. parallel slave port data. rd5/psp5 rd5 psp5 51 i/o i/o st ttl digital i/o. parallel slave port data. rd6/psp6 rd6 psp6 50 i/o i/o st ttl digital i/o. parallel slave port data. rd7/psp7 rd7 psp7 49 i/o i/o st ttl digital i/o. parallel slave port data. table 1-2: pic18f6310/6410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit ccp2mx is set. 2: alternate assignment for ccp2 when configuration bit ccp2mx is cleared.
? 2004 microchip technology inc. preliminary ds39635a-page 17 pic18f6310/6410/8310/8410 porte is a bidirectional i/o port. re0/rd re0 rd 2 i/o i st ttl digital i/o. read control for parallel slave port. re1/wr re1 wr 1 i/o i st ttl digital i/o. write control for parallel slave port. re2/cs re2 cs 64 i/o i st ttl digital i/o. chip select control for parallel slave port. re3 63 i/o st digital i/o. re4 62 i/o st digital i/o. re5 61 i/o st digital i/o. re6 60 i/o st digital i/o. re7/ccp2 re7 ccp2 (2) 59 i/o i/o st st digital i/o. capture 2 input/compare 2 output/pwm 2 output. table 1-2: pic18f6310/6410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit ccp2mx is set. 2: alternate assignment for ccp2 when configuration bit ccp2mx is cleared.
pic18f6310/6410/8310/8410 ds39635a-page 18 preliminary ? 2004 microchip technology inc. portf is a bidirectional i/o port. rf0/an5 rf0 an5 18 i/o i st analog digital i/o. analog input 5. rf1/an6/c2out rf1 an6 c2out 17 i/o i o st analog ? digital i/o. analog input 6. comparator 2 output. rf2/an7/c1out rf2 an7 c1out 16 i/o i o st analog ? digital i/o. analog input 7. comparator 1 output. rf3/an8 rf3 an8 15 i/o i st analog digital i/o. analog input 8. rf4/an9 rf4 an9 14 i/o i st analog digital i/o. analog input 9. rf5/an10/cv ref rf5 an10 cv ref 13 i/o i o st analog analog digital i/o. analog input 10. comparator reference voltage output. rf6/an11 rf6 an11 12 i/o i st analog digital i/o. analog input 11. rf7/ss rf7 ss 11 i/o i st ttl digital i/o. spi slave select input. table 1-2: pic18f6310/6410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit ccp2mx is set. 2: alternate assignment for ccp2 when configuration bit ccp2mx is cleared.
? 2004 microchip technology inc. preliminary ds39635a-page 19 pic18f6310/6410/8310/8410 portg is a bidirectional i/o port. rg0/ccp3 rg0 ccp3 3 i/o i/o st st digital i/o. capture 3 input/compare 3 output/pwm 3 output. rg1/tx2/ck2 rg1 tx2 ck2 4 i/o o i/o st ? st digital i/o. ausart2 asynchronous transmit. ausart2 synchronous clock (see related rx2/dt2). rg2/rx2/dt2 rg2 rx2 dt2 5 i/o i i/o st st st digital i/o. ausart2 asynchronous receive. ausart2 synchronous data (see related tx2/ck2). rg3 6 i/o st digital i/o. rg4 8 i/o st digital i/o. rg5 see rg5/mclr /v pp pin. v ss 9, 25, 41, 56 p ? ground reference for logic and i/o pins. v dd 10, 26, 38, 57 p ? positive supply for logic and i/o pins. av ss 20 p ? ground reference for analog modules. av dd 19 p ? positive supply for analog modules. table 1-2: pic18f6310/6410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for ccp2 when configuration bit ccp2mx is set. 2: alternate assignment for ccp2 when configuration bit ccp2mx is cleared.
pic18f6310/6410/8310/8410 ds39635a-page 20 preliminary ? 2004 microchip technology inc. table 1-3: pic18f8310/8410 pinout i/o descriptions pin name pin number pin type buffer type description tqfp rg5/mclr /v pp rg5 mclr v pp 9 i i p st st master clear (input) or programming voltage (input). digital input. master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. osc1/clki/ra7 osc1 clki ra7 49 i i i/o st cmos ttl oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode, cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 50 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for ccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for ccp2 when ccp2mx is cleared (microcontroller mode only).
? 2004 microchip technology inc. preliminary ds39635a-page 21 pic18f6310/6410/8310/8410 porta is a bidirectional i/o port. ra0/an0 ra0 an0 30 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 29 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 28 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 27 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 34 i/o i st/od st digital i/o. open-drain when configured as output. timer0 external clock input. ra5/an4/hlvdin ra5 an4 hlvdin 33 i/o i i ttl analog analog digital i/o. analog input 4. high/low-voltage detect input. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. table 1-3: pic18f8310/8410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for ccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for ccp2 when ccp2mx is cleared (microcontroller mode only).
pic18f6310/6410/8310/8410 ds39635a-page 22 preliminary ? 2004 microchip technology inc. portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0 rb0 int0 58 i/o i ttl st digital i/o. external interrupt 0. rb1/int1 rb1 int1 57 i/o i ttl st digital i/o. external interrupt 1. rb2/int2 rb2 int2 56 i/o i ttl st digital i/o. external interrupt 2. rb3/int3/ccp2 rb3 int3 ccp2 (1) 55 i/o i o ttl st analog digital i/o. external interrupt 3. capture 2 input/compare 2 output/pwm 2 output. rb4/kbi0 rb4 kbi0 54 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb5/kbi1 rb5 kbi1 53 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb6/kbi2/pgc rb6 kbi2 pgc 52 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 47 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-3: pic18f8310/8410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for ccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for ccp2 when ccp2mx is cleared (microcontroller mode only).
? 2004 microchip technology inc. preliminary ds39635a-page 23 pic18f6310/6410/8310/8410 portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 36 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 (2) 35 i/o i i/o st cmos st digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm 2 output. rc2/ccp1 rc2 ccp1 43 i/o i/o st st digital i/o. capture 1 input/compare 1 output/pwm 1 output. rc3/sck/scl rc3 sck scl 44 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi? mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi/sda rc4 sdi sda 45 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 46 i/o o st ? digital i/o. spi data out. rc6/tx1/ck1 rc6 tx1 ck1 37 i/o o i/o st ? st digital i/o. eusart1 asynchronous transmit. eusart1 synchronous clock (see related rx1/dt1). rc7/rx1/dt1 rc7 rx1 dt1 38 i/o i i/o st st st digital i/o. eusart1 asynchronous receive. eusart1 synchronous data (see related tx1/ck1). table 1-3: pic18f8310/8410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for ccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for ccp2 when ccp2mx is cleared (microcontroller mode only).
pic18f6310/6410/8310/8410 ds39635a-page 24 preliminary ? 2004 microchip technology inc. portd is a bidirectional i/o port. rd0/ad0/psp0 rd0 ad0 psp0 72 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 0. parallel slave port data. rd1/ad1/psp1 rd1 ad1 psp1 69 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 1. parallel slave port data. rd2/ad2/psp2 rd2 ad2 psp2 68 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 2. parallel slave port data. rd3/ad3/psp3 rd3 ad3 psp3 67 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 3. parallel slave port data. rd4/ad4/psp4 rd4 ad4 psp4 66 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 4. parallel slave port data. rd5/ad5/psp5 rd5 ad5 psp5 65 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 5. parallel slave port data. rd6/ad6/psp6 rd6 ad6 psp6 64 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 6. parallel slave port data. rd7/ad7/psp7 rd7 ad7 psp7 63 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 7. parallel slave port data. table 1-3: pic18f8310/8410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for ccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for ccp2 when ccp2mx is cleared (microcontroller mode only).
? 2004 microchip technology inc. preliminary ds39635a-page 25 pic18f6310/6410/8310/8410 porte is a bidirectional i/o port. re0/ad8/rd re0 ad8 rd 4 i/o i/o i st ttl ttl digital i/o. external memory address/data 8. read control for parallel slave port. re1/ad9/wr re1 ad9 wr 3 i/o i/o i st ttl ttl digital i/o. external memory address/data 9. write control for parallel slave port. re2/ad10/cs re2 ad10 cs 78 i/o i/o i st ttl ttl digital i/o. external memory address/data 10. chip select control for parallel slave port. re3/ad11 re3 ad11 77 i/o i/o st ttl digital i/o. external memory address/data 11. re4/ad12 re4 ad12 76 i/o i/o st ttl digital i/o. external memory address/data 12. re5/ad13 re5 ad13 75 i/o i/o st ttl digital i/o. external memory address/data 13. re6/ad14 re6 ad14 74 i/o i/o st ttl digital i/o. external memory address/data 14. re7/ccp2/ad15 re7 ccp2 (3) ad15 73 i/o i/o i/o st st ttl digital i/o. capture 2 input/compare 2 output/pwm 2 output. external memory address/data 15. table 1-3: pic18f8310/8410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for ccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for ccp2 when ccp2mx is cleared (microcontroller mode only).
pic18f6310/6410/8310/8410 ds39635a-page 26 preliminary ? 2004 microchip technology inc. portf is a bidirectional i/o port. rf0/an5 rf0 an5 24 i/o i st analog digital i/o. analog input 5. rf1/an6/c2out rf1 an6 c2out 23 i/o i o st analog ? digital i/o. analog input 6. comparator 2 output. rf2/an7/c1out rf2 an7 c1out 18 i/o i o st analog ? digital i/o. analog input 7. comparator 1 output. rf3/an8 rf3 an8 17 i/o i st analog digital i/o. analog input 8. rf4/an9 rf4 an9 16 i/o i st analog digital i/o. analog input 9. rf5/an10/cv ref rf5 an10 cv ref 15 i/o i o st analog analog digital i/o. analog input 10. comparator reference voltage output. rf6/an11 rf6 an11 14 i/o i st analog digital i/o. analog input 11. rf7/ss rf7 ss 13 i/o i st ttl digital i/o. spi slave select input. table 1-3: pic18f8310/8410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for ccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for ccp2 when ccp2mx is cleared (microcontroller mode only).
? 2004 microchip technology inc. preliminary ds39635a-page 27 pic18f6310/6410/8310/8410 portg is a bidirectional i/o port. rg0/ccp3 rg0 ccp3 5 i/o i/o st st digital i/o. capture 3 input/compare 3 output/pwm 3 output. rg1/tx2/ck2 rg1 tx2 ck2 6 i/o o i/o st ? st digital i/o. ausart2 asynchronous transmit. ausart2 synchronous clock (see related rx2/dt2). rg2/rx2/dt2 rg2 rx2 dt2 7 i/o i i/o st st st digital i/o. ausart2 asynchronous receive. ausart2 synchronous data (see related tx2/ck2). rg3 8 i/o st digital i/o. rg4 10 i/o st digital i/o. rg5 see rg5/mclr /v pp pin. porth is a bidirectional i/o port. rh0/ad16 rh0 ad16 79 i/o i/o st ttl digital i/o. external memory address/data 16. rh1/ad17 rh1 ad17 80 i/o i/o st ttl digital i/o. external memory address/data 17. rh2/ad18 rh2 ad18 1 i/o i/o st ttl digital i/o. external memory address/data 18. rh3/ad19 rh3 ad19 2 i/o i/o st ttl digital i/o. external memory address/data 19. rh4 22 i/o st digital i/o. rh5 21 i/o st digital i/o. rh6 20 i/o st digital i/o. rh7 19 i/o st digital i/o. table 1-3: pic18f8310/8410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for ccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for ccp2 when ccp2mx is cleared (microcontroller mode only).
pic18f6310/6410/8310/8410 ds39635a-page 28 preliminary ? 2004 microchip technology inc. portj is a bidirectional i/o port. rj0/ale rj0 ale 62 i/o o st ? digital i/o. external memory address latch enable. rj1/oe rj1 oe 61 i/o o st ? digital i/o. external memory output enable. rj2/wrl rj2 wrl 60 i/o o st ? digital i/o. external memory write low control. rj3/wrh rj3 wrh 59 i/o o st ? digital i/o. external memory write high control. rj4/ba0 rj4 ba0 39 i/o o st ? digital i/o. external memory byte address 0 control. rj5/ce rj4 ce 40 i/o o st ? digital i/o external memory chip enable control. rj6/lb rj6 lb 41 i/o o st ? digital i/o. external memory low byte control. rj7/ub rj7 ub 42 i/o o st ? digital i/o. external memory high byte control. v ss 11, 31, 51, 70 p ? ground reference for logic and i/o pins. v dd 12, 32, 48, 71 p ? positive supply for logic and i/o pins. av ss 26 p ? ground reference for analog modules. av dd 25 p ? positive supply for analog modules. table 1-3: pic18f8310/8410 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for ccp2 when configuration bit ccp2mx is cleared (all operating modes except microcontroller mode). 2: default assignment for ccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for ccp2 when ccp2mx is cleared (microcontroller mode only).
? 2004 microchip technology inc. preliminary ds39635a-page 29 pic18f6310/6410/8310/8410 2.0 oscillator configurations 2.1 oscillator types pic18f6310/6410/8310/8410 devices can be operated in ten different oscillator modes. the user can program the configuration bits, fosc3:fosc0, in configuration register 1h to select one of these ten modes: 1. lp low-power crystal 2. xt crystal/resonator 3. hs high-speed crystal/resonator 4. hspll high-speed crystal/resonator with pll enabled 5. rc external resistor/capacitor with f osc /4 output on ra6 6. rcio external resistor/capacitor with i/o on ra6 7. intio1 internal oscillator with f osc /4 output on ra6 and i/o on ra7 8. intio2 internal oscillator with i/o on ra6 and ra7 9. ec external clock with f osc /4 output 10. ecio external clock with i/o on ra6 2.2 crystal oscillator/ceramic resonators in xt, lp, hs or hspll oscillator modes, a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation. figure 2-1 shows the pin connections. the oscillator design requires the use of a parallel cut crystal. figure 2-1: crystal/ceramic resonator operation (xt, lp, hs or hspll configuration) table 2-1: capacitor selection for ceramic resonators note: use of a series cut crystal may give a fre- quency out of the crystal manufacturer?s specifications. typical capacitor values used: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 56 pf 47 pf 33 pf 56 pf 47 pf 33 pf hs 8.0 mhz 16.0 mhz 27 pf 22 pf 27 pf 22 pf capacitor values are for design guidance only. these capacitors were tested with the resonators listed below for basic start-up and operation. these values are not optimized . different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes following table 2-2 for additional information. resonators used: 455 khz 4.0 mhz 2.0 mhz 8.0 mhz 16.0 mhz note 1: see table 2-1 and table 2-2 for initial values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the oscillator mode chosen. c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep to logic pic18fxxxx r s (2) internal
pic18f6310/6410/8310/8410 ds39635a-page 30 preliminary ? 2004 microchip technology inc. table 2-2: capacitor selection for crystal oscillator an external clock source may also be connected to the osc1 pin in the hs mode, as shown in figure 2-2. figure 2-2: external clock input operation (hs oscillator configuration) 2.3 external clock input the ec and ecio oscillator modes require an external clock source to be connected to the osc1 pin. there is no oscillator start-up time required after a power-on reset or after an exit from sleep mode. in the ec oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-3 shows the pin connections for the ec oscillator mode. figure 2-3: external clock input operation (ec configuration) the ecio oscillator mode functions like the ec mode, except that the osc2 pin becomes an additional gen- eral purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 2-4 shows the pin connections for the ecio oscillator mode. figure 2-4: external clock input operation (ecio configuration) osc type crystal freq typical capacitor values tested: c1 c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 1 mhz 33 pf 33 pf 4 mhz 27 pf 27 pf hs 4 mhz 27 pf 27 pf 8 mhz 22 pf 22 pf 20 mhz 15 pf 15 pf capacitor values are for design guidance only. these capacitors were tested with the crystals listed below for basic start-up and operation. these values are not optimized. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes following this table for additional information. crystals used: 32 khz 4 mhz 200 khz 8 mhz 1 mhz 20 mhz note 1: higher capacitance increases the stability of oscillator, but also increases the start-up time. 2: when operating below 3v v dd , or when using certain ceramic resonators at any voltage, it may be necessary to use the hs mode or switch to a crystal oscillator. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: rs may be required to avoid overdriving crystals with low drive level specification. 5: always verify oscillator performance over the v dd and temperature range that is expected for the application. osc1 osc2 open clock from ext. system pic18fxxxx (hs mode) osc1/clki osc2/clko f osc /4 clock from ext. system pic18fxxxx osc1/clki i/o (osc2) ra6 clock from ext. system pic18fxxxx
? 2004 microchip technology inc. preliminary ds39635a-page 31 pic18f6310/6410/8310/8410 2.4 rc oscillator for timing insensitive applications, the ?rc? and ?rcio? device options offer additional cost savings. the actual oscillator frequency is a function of several factors: supply voltage values of the external resistor (r ext ) and capacitor (c ext ) operating temperature given the same device, operating voltage and temperature and component values, there will also be unit-to-unit frequency variations. these are due to factors such as: normal manufacturing variation difference in lead frame capacitance between package types (especially for low c ext values) variations within the tolerance of limits of r ext and c ext in the rc oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-5 shows how the r/c combination is connected. figure 2-5: rc oscillator mode the rcio oscillator mode (figure 2-6) functions like the rc mode, except that the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 2-6: rcio oscillator mode 2.5 pll frequency multiplier a phase locked loop (pll) circuit is provided as an option for users who want to use a lower frequency oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. this may be useful for customers who are concerned with emi due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator. 2.5.1 hspll oscillator mode the hspll mode makes use of the hs oscillator mode for frequencies up to 10 mhz. a pll then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 mhz. the pll is only available to the crystal oscillator when the fosc3:fosc0 configuration bits are programmed for hspll mode (= 0110 ). figure 2-7: pll block diagram (hs mode) 2.5.2 pll and intosc the pll is also available to the internal oscillator block in selected oscillator modes. in this configuration, the pll is enabled in software and generates a clock out- put of up to 32 mhz. the operation of intosc with the pll is described in section 2.6.4 ?pll in intosc modes? . osc2/clko c ext r ext pic18fxxxx osc1 f osc /4 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20 pf c ext r ext pic18fxxxx osc1 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20 pf i/o (osc2) ra6 mux vco loop filter crystal oscillator osc2 osc1 pll enable f in f out sysclk phase comparator hs oscillator enable 4 (from configuration register 1h) hs mode
pic18f6310/6410/8310/8410 ds39635a-page 32 preliminary ? 2004 microchip technology inc. 2.6 internal oscillator block the pic18f6310/6410/8310/8410 devices include an internal oscillator block, which generates two different clock signals; either can be used as the microcontrol- ler?s clock source. this may eliminate the need for external oscillator circuits on the osc1 and/or osc2 pins. the main output (intosc) is an 8 mhz clock source, which can be used to directly drive the device clock. it also drives a postscaler, which can provide a range of clock frequencies from 31 khz to 4 mhz. the intosc output is enabled when a clock frequency from 125 khz to 8 mhz is selected. the other clock source is the internal rc oscillator (intrc), which provides a nominal 31 khz output. intrc is enabled if it is selected as the device clock source; it is also enabled automatically when any of the following are enabled: power-up timer fail-safe clock monitor watchdog timer two-speed start-up these features are discussed in greater detail in section 23.0 ?special features of the cpu? . the clock source frequency (intosc direct, intrc direct or intosc postscaler) is selected by configuring the ircf bits of the osccon register (register 2-2). 2.6.1 intio modes using the internal oscillator as the clock source elimi- nates the need for up to two external oscillator pins, which can then be used for digital i/o. two distinct configurations are available: in intio1 mode, the osc2 pin outputs f osc /4, while osc1 functions as ra7 for digital input and output. in intio2 mode, osc1 functions as ra7 and osc2 functions as ra6, both for digital input and output. 2.6.2 intosc output frequency the internal oscillator block is calibrated at the factory to produce an intosc output frequency of 8.0 mhz. the intrc oscillator operates independently of the intosc source. any changes in intosc across voltage and temperature are not necessarily reflected by changes in intrc and vice versa. 2.6.3 osctune register the internal oscillator?s output has been calibrated at the factory, but can be adjusted in the user?s applica- tion. this is done by writing to the osctune register (register 2-1). the tuning sensitivity is constant throughout the tuning range. when the osctune register is modified, the intosc and intrc frequencies will begin shifting to the new frequency. the intrc clock will reach the new frequency within 8 clock cycles (approximately 8*32 s = 256 s). the intosc clock will stabilize within 1 ms. code execution continues during this shift. there is no indication that the shift has occurred. the osctune register also implements the intsrc and pllen bits, which control certain features of the internal oscillator block. the intsrc bit allows users to select which internal oscillator provides the clock source when the 31 khz frequency option is selected. this is covered in greater detail in section 2.7.1 ?oscillator control register? . the pllen bit controls the operation of the frequency multiplier, pll, in internal oscillator modes. 2.6.4 pll in intosc modes the 4x frequency multiplier can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with an internal oscillator. when enabled, the pll produces a clock speed of up to 32 mhz. unlike hspll mode, the pll is controlled through software. the control bit, pllen (osctune<6>), is used to enable or disable its operation. the pll is available when the device is configured to use the internal oscillator block as its primary clock source (fosc3:fosc0 = 1001 or 1000 ). additionally, the pll will only function when the selected output frequency is either 4 mhz or 8 mhz (osccon<6:4> = 111 or 110 ). if both of these conditions are not met, the pll is disabled. the pllen control bit is only functional in those inter- nal oscillator modes where the pll is available. in all other modes, it is forced to ? 0 ? and is effectively unavailable. 2.6.5 intosc frequency drift the factory calibrates the internal oscillator block out- put (intosc) for 8 mhz. however, this frequency may drift as v dd or temperature changes, which can affect the controller operation in a variety of ways. it is possi- ble to adjust the intosc frequency by modifying the value in the ostune register. this has no effect on the intrc clock source frequency. tuning the intosc source requires knowing when to make the adjustment, in which direction it should be made and in some cases, how large a change is needed. three examples follow, but other techniques may be used.
? 2004 microchip technology inc. preliminary ds39635a-page 33 pic18f6310/6410/8310/8410 2.6.5.1 compensating with the ausart an adjustment may be required when the ausart begins to generate framing errors or receives data with errors while in asynchronous mode. framing errors indicate that the device clock frequency is too high; to adjust for this, decrement the value in ostune to reduce the clock frequency. on the other hand, errors in data may suggest that the clock speed is too low; to compensate, increment ostune to increase the clock frequency. 2.6.5.2 compensating with the timers this technique compares device clock speed to some reference clock. two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the timer1 oscillator. both timers are cleared, but the timer clocked by the reference generates interrupts. when an interrupt occurs, the internally clocked timer is read and both timers are cleared. if the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. to adjust for this, decrement the osctune register. 2.6.5.3 compensating with the timers a ccp module can use free running timer1 (or timer3), clocked by the internal oscillator block and an external event with a known period (i.e., ac power frequency). the time of the first event is captured in the ccprxh:ccprxl registers and is recorded. when the second event causes a capture, the time of the first event is subtracted from the time of the second event. since the period of the external event is known, the time difference between events can be calculated. if the measured time is much greater than the calculated time, then the internal oscillator block is running too fast; to compensate, decrement the ostune register. if the measured time is much less than the calculated time, then the internal oscillator block is running too slow; to compensate, increment the ostune register. register 2-1: osctune: oscillator tuning register r/w-0 r/w-0 (1) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 intsrc pllen (1) ? tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 bit 7 intsrc: internal oscillator low-frequency source select bit 1 = 31.25 khz device clock derived from 8 mhz intosc source (divide-by-256 enabled) 0 = 31 khz device clock derived directly from intrc internal oscillator bit 6 pllen: frequency multiplier pll for intosc enable bit (1) 1 = pll enabled for intosc (4 mhz and 8 mhz only) 0 = pll disabled note 1: available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ? 0 ?. see section 2.6.4 ?pll in intosc modes? for details. bit 5 unimplemented: read as ? 0 ? bit 4-0 tun4:tun0: frequency tuning bits 01111 = maximum frequency 00001 00000 = center frequency. oscillator module is running at the calibrated frequency. 11111 10000 = minimum frequency legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 34 preliminary ? 2004 microchip technology inc. 2.7 clock sources and oscillator switching like previous pic18 devices, the pic18f6310/6410/8310/8410 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source. pic18f6310/6410/8310/8410 devices offer two alternate clock sources. when an alternate clock source is enabled, the various power managed operating modes are available. essentially, there are three clock sources for these devices: primary oscillators secondary oscillators internal oscillator block the primary oscillators include the external crystal and resonator modes, the external rc modes, the external clock modes and the internal oscillator block. the particular mode is defined by the fosc3:fosc0 configuration bits. the details of these modes are covered earlier in this chapter. the secondary oscillators are those external sources not connected to the osc1 or osc2 pins. these sources may continue to operate even after the controller is placed in a power managed mode. pic18f6310/6410/8310/8410 devices offer the timer1 oscillator as a secondary oscillator. this oscillator, in all power managed modes, is often the time base for functions such as a real-time clock. most often, a 32.768 khz watch crystal is connected between the rc0/t1oso/t13cki and rc1/t1osi pins. like the lp mode oscillator circuit, loading capacitors are also connected from each pin to ground. the timer1 oscillator is discussed in greater detail in section 12.3 ?timer1 oscillator? . in addition to being a primary clock source, the internal oscillator block is available as a power managed mode clock source. the intrc source is also used as the clock source for several special features, such as the wdt and fail-safe clock monitor. the clock sources for the pic18f6310/6410/8310/8410 devices are shown in figure 2-8. see section 23.0 ?special features of the cpu? for configuration register details. figure 2-8: pic18f6310/6410/8310/8410 clock diagram pic18f6x10/8x10 4 x pll fosc3:fosc0 secondary oscillator t1oscen enable oscillator t1oso t1osi clock source option for other modules osc1 osc2 sleep hspll, intosc/pll lp, xt, hs, rc, ec t1osc cpu peripherals idlen postscaler mux mux 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 125 khz 250 khz osccon<6:4> 111 110 101 100 011 010 001 000 31 khz intrc source internal oscillator block wdt, pwrt, fscm 8 mhz internal oscillator (intosc) osccon<6:4> clock control osccon<1:0> source 8 mhz 31 khz (intrc) osctune<6> 0 1 osctune<7> and two-speed start-up primary oscillator
? 2004 microchip technology inc. preliminary ds39635a-page 35 pic18f6310/6410/8310/8410 2.7.1 oscillator control register the osccon register (register 2-2) controls several aspects of the device clock?s operation, both in full power operation and in power managed modes. the system clock select bits, scs1:scs0, select the clock source. the available clock sources are the pri- mary clock (defined by the fosc:fosc0 configuration bits), the secondary clock (timer1 oscillator) and the internal oscillator block. the clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. the scs bits are cleared on all forms of reset. the internal oscillator frequency select bits, ircf2:ircf0, select the frequency output of the internal oscillator block to drive the device clock. the choices are the intrc source, the intosc source (8 mhz) or one of the frequencies derived from the intosc postscaler (31.25 khz to 4 mhz). if the internal oscillator block is supplying the device clock, changing the states of these bits will have an immediate change on the internal oscillator?s output. when an output frequency of 31 khz is selected (ircf2:ircf0 = 000 ), users may choose which inter- nal oscillator acts as the source. this is done with the intsrc bit in the osctune register (osctune<7>). setting this bit selects intosc as a 31.25 khz clock source by enabling the divide-by-256 output of the intosc postscaler. clearing intsrc selects intrc (nominally 31 khz) as the clock source. this option allows users to select the tunable and more precise intosc as a clock source, while maintaining power savings with a very low clock speed. regardless of the setting of intsrc, intrc always remains the clock source for features such as the watchdog timer and the fail-safe clock monitor. the osts, iofs and t1run bits indicate which clock source is currently providing the device clock. the osts bit indicates that the oscillator start-up timer has timed out and the primary clock is providing the device clock in primary clock modes. the iofs bit indi- cates when the internal oscillator block has stabilized and is providing the device clock in rc clock modes. the t1run bit (t1con<6>) indicates when the timer1 oscillator is providing the device clock in secondary clock modes. in power managed modes, only one of these three bits will be set at any time. if none of these bits are set, the intrc is providing the clock, or the internal oscillator block has just started and is not yet stable. the idlen bit determines if the device goes into sleep mode or one of the idle modes when the sleep instruction is executed. the use of the flag and control bits in the osccon register is discussed in more detail in section 3.0 ?power managed modes? . 2.7.2 oscillator transitions pic18f6310/6410/8310/8410 devices contain circuitry to prevent clock ?glitches? when switching between clock sources. a short pause in the device clock occurs during the clock switch. the length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. this formula assumes that the new clock source is stable. clock transitions are discussed in greater detail in section 3.1.2 ?entering power managed modes? . note 1: the timer1 oscillator must be enabled to select the secondary clock source. the timer1 oscillator is enabled by setting the t1oscen bit in the timer1 control regis- ter (t1con<3>). if the timer1 oscillator is not enabled, then any attempt to select a secondary clock source when executing a sleep instruction will be ignored. 2: it is recommended that the timer1 oscillator be operating and stable before executing the sleep instruction or a very long delay may occur while the timer1 oscillator starts.
pic18f6310/6410/8310/8410 ds39635a-page 36 preliminary ? 2004 microchip technology inc. register 2-2: osccon: oscillator co ntrol register r/w-0 r/w-1 r/w-0 r/w-0 r (1) r-0 r/w-0 r/w-0 idlen ircf2 ircf1 ircf0 osts iofs scs1 scs0 bit 7 bit 0 bit 7 idlen: idle enable bit 1 = device enters idle mode on sleep instruction 0 = device enters sleep mode on sleep instruction bit 6-4 ircf2:ircf0: internal oscillator frequency select bits 111 = 8 mhz (intosc drives clock directly) 110 = 4 mhz 101 = 2 mhz 100 = 1 mhz (3) 011 = 500 khz 010 = 250 khz 001 = 125 khz 000 = 31 khz (from either intosc/256 or intrc directly) (2) bit 3 osts: oscillator start-up time-out status bit (1) 1 = oscillator start-up timer time-out has expired; primary oscillator is running 0 = oscillator start-up timer time-out is running; primary oscillator is not ready bit 2 iofs: intosc frequency stable bit 1 = intosc frequency is stable 0 = intosc frequency is not stable bit 1-0 scs1:scs0: system clock select bits 1x = internal oscillator block 01 = timer1 oscillator 00 = primary oscillator note 1: depends on state of the ieso configuration bit. 2: source selected by the intsrc bit (osctune<7>), see section 2.6.3 ?osctune register? . 3: default output frequency of intosc on reset. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39635a-page 37 pic18f6310/6410/8310/8410 2.8 effects of power managed modes on the various clock sources when pri_idle mode is selected, the designated primary oscillator continues to run without interruption. for all other power managed modes, the oscillator using the osc1 pin is disabled. the osc1 pin (and osc2 pin, if used by the oscillator) will stop oscillating. in secondary clock modes (sec_run and sec_idle), the timer1 oscillator is operating and providing the device clock. the timer1 oscillator may also run in all power managed modes if required to clock timer1 or timer3. in internal oscillator modes (rc_run and rc_idle), the internal oscillator block provides the device clock source. the 31 khz intrc output can be used directly to provide the clock and may be enabled to support var- ious special features, regardless of the power managed mode (see section 23.2 ?watchdog timer (wdt)? through section 23.4 ?fail-safe clock monitor? for more information on wdt, fail-safe clock monitor and two-speed start-up). the intosc output at 8 mhz may be used directly to clock the device, or may be divided down by the postscaler. the intosc output is disabled if the clock is provided directly from the intrc output. if the sleep mode is selected, all clock sources are stopped. since all the transistor switching currents have been stopped, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the intrc is required to support wdt operation. the timer1 oscillator may be operating to support a real-time clock. other features may be operating that do not require a device clock source (i.e., ssp slave, psp, intn pins and others). peripherals that may add significant current consumption are listed in section 26.2 ?dc characteristics: power-down and supply current? . 2.9 power-up delays power-up delays are controlled by two timers, so that no external reset circuitry is required for most applications. the delays ensure that the device is kept in reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. for additional information on power-up delays, see section 4.5 ?device reset timers? . the first timer is the power-up timer (pwrt), which provides a fixed delay on power-up (parameter 33, table 26-12). it is enabled by clearing (= 0 ) the pwrten configuration bit. the second timer is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable (lp, xt and hs modes). the ost does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. when the hspll oscillator mode is selected, the device is kept in reset for an additional 2 ms, following the hs mode ost delay, so the pll can lock to the incoming clock frequency. there is a delay of interval t csd (parameter 38, table 26-12) following por while the controller becomes ready to execute instructions. this delay runs concurrently with any other delays. this may be the only delay that occurs when any of the ec, rc or intio modes are used as the primary clock source. table 2-3: osc1 and osc2 pin states in sleep mode oscillator mode osc1 pin osc2 pin rc, intio1 floating, external resistor should pull high at logic low (clock/4 output) rcio, intio2 floating, external resistor should pull high configured as porta, bit 6 ecio floating, pulled by external clock configured as porta, bit 6 ec floating, pulled by external clock at logic low (clock/4 output) lp, xt and hs feedback inverter disabled at quiescent voltage level feedback inverter disabled at quiescent voltage level note: see table 4-2 in section 4.0 ?reset? for time-outs due to sleep and mclr reset.
pic18f6310/6410/8310/8410 ds39635a-page 38 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 39 pic18f6310/6410/8310/8410 3.0 power managed modes pic18f6310/6410/8310/8410 devices offer a total of seven operating modes for more efficient power management. these modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). there are three categories of power managed modes: sleep mode idle modes run modes these categories define which portions of the device are clocked and sometimes, what speed. the run and idle modes may use any of the three available clock sources (primary, secondary or intosc multiplexer); the sleep mode does not use a clock source. the power managed modes include several power-saving features. one of these is the clock switching feature, offered in other pic18 devices, allowing the controller to use the timer1 oscillator in place of the primary oscillator. also included is the sleep mode, offered by all picmicro ? devices, where all device clocks are stopped. 3.1 selecting power managed modes selecting a power managed mode requires deciding if the cpu is to be clocked or not and selecting a clock source. the idlen bit controls cpu clocking, while the scs1:scs0 bits select a clock source. the individual modes, bit settings, clock sources and affected modules are summarized in table 3-1. 3.1.1 clock sources the scs1:scs0 bits allow the selection of one of three clock sources for power managed modes. they are: the primary clock, as defined by the fosc3:fosc0 configuration bits the secondary clock (the timer1 oscillator) the internal oscillator block (for rc modes) 3.1.2 entering power managed modes entering power managed run mode, or switching from one power managed mode to another, begins by loading the osccon register. the scs1:scs0 bits select the clock source and determine which run or idle mode is being used. changing these bits causes an immediate switch to the new clock source, assuming that it is running. the switch may also be subject to clock transition delays. these are discussed in section 3.1.3 ?clock transitions and status indicators? and subsequent sections. entry to the power managed idle or sleep modes is triggered by the execution of a sleep instruction. the actual mode that results depends on the status of the idlen bit. depending on the current mode and the mode being switched to, a change to a power managed mode does not always require setting all of these bits. many transi- tions may be done by changing the oscillator select bits, or changing the idlen bit prior to issuing a sleep instruction. if the idlen bit is already configured correctly, it may only be necessary to perform a sleep instruction to switch to the desired mode. table 3-1: power managed modes mode osccon bits module clocking available clock and oscillator source idlen (1) <7> scs1:scs0 <1:0> cpu peripherals sleep 0 n/a off off none ? all clocks are disabled pri_run n/a 00 clocked clocked primary ? lp, xt, hs, hspll, rc, ec, intrc (2) this is the normal full power execution mode. sec_run n/a 01 clocked clocked secondary ? timer1 oscillator rc_run n/a 1x clocked clocked internal oscillator block (2) pri_idle 100 off clocked primary ? lp, xt, hs, hspll, rc, ec sec_idle 101 off clocked secondary ? timer1 oscillator rc_idle 11x off clocked internal oscillator block (2) note 1: idlen reflects its value when the sleep instruction is executed. 2: includes intosc and intosc postsc aler, as well as the intrc source.
pic18f6310/6410/8310/8410 ds39635a-page 40 preliminary ? 2004 microchip technology inc. 3.1.3 clock transitions and status indicators the length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. this formula assumes that the new clock source is stable. three bits indicate the current clock source and its status. they are: osts (osccon<3>) iofs (osccon<2>) t1run (t1con<6>) in general, only one of these bits will be set while in a given power managed mode. when the osts bit is set, the primary clock is providing the device clock. when the iofs bit is set, the intosc output is provid- ing a stable 8 mhz clock source to a divider that actu- ally drives the device clock. when the t1run bit is set, the timer1 oscillator is providing the clock. if none of these bits are set, then either the intrc clock source is clocking the device or the intosc source is not yet stable. if the internal oscillator block is configured as the primary clock source by the fosc3:fosc0 configuration bits, then both the osts and iofs bits may be set when in pri_run or pri_idle modes. this indicates that the primary clock (intosc output) is generating a stable 8 mhz output. entering another power managed rc mode at the same frequency would clear the osts bit. 3.1.4 multiple sleep commands the power managed mode that is invoked with the sleep instruction is determined by the setting of the idlen bit at the time the instruction is executed. if another sleep instruction is executed, the device will enter the power managed mode specified by idlen at that time. if idlen has changed, the device will enter the new power managed mode specified by the new setting. 3.2 run modes in the run modes, clocks to both the core and peripherals are active. the difference between these modes is the clock source. 3.2.1 pri_run mode the pri_run mode is the normal full power execution mode of the microcontroller. this is also the default mode upon a device reset unless two-speed start-up is enabled (see section 23.3 ?two-speed start-up? for details). in this mode, the osts bit is set. the iofs bit may be set if the internal oscillator block is the primary clock source (see section 2.7.1 ?oscillator control register? ). 3.2.2 sec_run mode the sec_run mode is the compatible mode to the ?clock switching? feature offered in other pic18 devices. in this mode, the cpu and peripherals are clocked from the timer1 oscillator. this gives users the option of lower power consumption while still using a high accuracy clock source. sec_run mode is entered by setting the scs1:scs0 bits to ? 01 ?. the device clock source is switched to the timer1 oscillator (see figure 3-1), the primary oscillator is shut down, the t1run bit (t1con<6>) is set and the osts bit is cleared. on transitions from sec_run mode to pri_run, the peripherals and cpu continue to be clocked from the timer1 oscillator while the primary clock is started. when the primary clock becomes ready, a clock switch back to the primary clock occurs (see figure 3-2). when the clock switch is complete, the t1run bit is cleared, the osts bit is set and the primary clock is providing the clock. the idlen and scs bits are not affected by the wake-up; the timer1 oscillator continues to run. note 1: caution should be used when modifying a single ircf bit. if v dd is less than 3v, it is possible to select a higher clock speed than is supported by the low v dd . improper device operation may result if the v dd /f osc specifications are violated. 2: executing a sleep instruction does not necessarily place the device into sleep mode. it acts as the trigger to place the controller into either the sleep mode or one of the idle modes, depending on the setting of the idlen bit. note: the timer1 oscillator should already be running prior to entering sec_run mode. if the t1oscen bit is not set when the scs1:scs0 bits are set to ? 01 ?, entry to sec_run mode will not occur. if the timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result.
? 2004 microchip technology inc. preliminary ds39635a-page 41 pic18f6310/6410/8310/8410 figure 3-1: transition timing for entry to sec_run mode figure 3-2: transition timing from sec_run mode to pri_run mode (hspll) q4 q3 q2 osc1 peripheral program q1 t1osi q1 counter clock cpu clock pc + 2 pc 123 n-1n clock transition q4 q3 q2 q1 q3 q2 pc + 4 q1 q3 q4 osc1 peripheral program pc t1osi pll clock q1 pc + 4 q2 output q3 q4 q1 cpu clock pc + 2 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. scs1:scs0 bits changed t pll (1) 12 n-1 n clock osts bit set transition t ost (1)
pic18f6310/6410/8310/8410 ds39635a-page 42 preliminary ? 2004 microchip technology inc. 3.2.3 rc_run mode in rc_run mode, the cpu and peripherals are clocked from the internal oscillator block using the intosc multiplexer and the primary clock is shut down. when using the intrc source, this mode provides the best power conservation of all the run modes, while still executing code. it works well for user applications which are not highly timing sensitive, or do not require high-speed clocks at all times. if the primary clock source is the internal oscillator block (either intrc or intosc), there are no distinguishable differences between pri_run and rc_run modes dur- ing execution. however, a clock switch delay will occur during entry to and exit from rc_run mode. therefore, if the primary clock source is the internal oscillator block, the use of rc_run mode is not recommended. this mode is entered by setting the scs1 bit to ? 1 ?. although it is ignored, it is recommended that the scs0 bit also be cleared; this is to maintain software compatibility with future devices. when the clock source is switched to the intosc multiplexer (see figure 3-3), the primary oscillator is shut down and the osts bit is cleared.the ircf bits may be modified at any time to immediately change the clock speed. if the ircf bits and the intsrc bit are all clear, the intosc output is not enabled and the iofs bit will remain clear; there will be no indication of the current clock source. the intrc source is providing the device clocks. if the ircf bits are changed from all clear (thus, enabling the intosc output), or if intsrc is set, the iofs bit becomes set after the intosc output becomes stable. clocks to the device continue while the intosc source stabilizes after an interval of t iobst . if the ircf bits were previously at a non-zero value, or if intsrc was set before setting scs1 and the intosc source was already stable, the iofs bit will remain set. on transitions from rc_run mode to pri_run, the device continues to be clocked from the intosc multiplexer while the primary clock is started. when the primary clock becomes ready, a clock switch to the primary clock occurs (see figure 3-4). when the clock switch is complete, the iofs bit is cleared, the osts bit is set and the primary clock is providing the device clock. the idlen and scs bits are not affected by the switch. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. figure 3-3: transition timing to rc_run mode figure 3-4: transition timing fr om rc_run mode to pri_run mode note: caution should be used when modifying a single ircf bit. if v dd is less than 3v, it is possible to select a higher clock speed than is supported by the low v dd . improper device operation may result if the v dd /f osc specifications are violated. q4 q3 q2 osc1 peripheral program q1 intrc q1 counter clock cpu clock pc + 2 pc 123 n-1n clock transition q4 q3 q2 q1 q3 q2 pc + 4 q1 q3 q4 osc1 peripheral program pc intosc pll clock q1 pc + 4 q2 output q3 q4 q1 cpu clock pc + 2 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. scs1:scs0 bits changed t pll (1) 12 n-1n clock osts bit set transition multiplexer t ost (1)
? 2004 microchip technology inc. preliminary ds39635a-page 43 pic18f6310/6410/8310/8410 3.3 sleep mode the power managed sleep mode in the pic18f6310/6410/8310/8410 devices is identical to the legacy sleep mode offered in all other picmicro ? devices. it is entered by clearing the idlen bit (the default state on device reset) and executing the sleep instruction. this shuts down the selected oscillator (see figure 3-5). all clock source status bits are cleared. entering the sleep mode from any other mode does not require a clock switch. this is because no clocks are needed once the controller has entered sleep. if the wdt is selected, the intrc source will continue to operate. if the timer1 oscillator is enabled, it will also continue to run. when a wake event occurs in sleep mode (by interrupt, reset or wdt time-out), the device will not be clocked until the primary clock source becomes ready (see figure 3-6), or it will be clocked from the internal oscillator block if either the two-speed start-up or the fail-safe clock monitor are enabled (see section 23.0 ?special features of the cpu? ). in either case, the osts bit is set when the primary clock is providing the device clocks. the idlen and scs bits are not affected by the wake-up. 3.4 idle modes the idle modes allow the controller?s cpu to be selectively shut down while the peripherals continue to operate. selecting a particular idle mode allows users to further manage power consumption. if the idlen bit is set to a ? 1 ? when a sleep instruction is executed, the peripherals will be clocked from the clock source selected using the scs1:scs0 bits; however, the cpu will not be clocked. the clock source status bits are not affected. setting idlen and execut- ing sleep provides a quick method of switching from a given run mode to its corresponding idle mode. if the wdt is selected, the intrc source will continue to operate. if the timer1 oscillator is enabled, it will also continue to run. since the cpu is not executing instructions, the only exits from any of the idle modes are by interrupt, wdt time-out or a reset. when a wake event occurs, cpu execution is delayed by an interval of t csd (parameter 38, table 26-12), while it becomes ready to execute code. when the cpu begins executing code, it resumes with the same clock source for the current idle mode. for example, when waking from rc_idle mode, the internal oscillator block will clock the cpu and peripherals (in other words, rc_run mode). the idlen and scs bits are not affected by the wake-up. while in any idle mode or the sleep mode, a wdt time-out will result in a wdt wake-up to the run mode currently specified by the scs1:scs0 bits. figure 3-5: transition timing for entry to sleep mode figure 3-6: transition timing for wake from sleep (hspll) q4 q3 q2 osc1 peripheral sleep program q1 q1 counter clock cpu clock pc + 2 pc q3 q4 q1 q2 osc1 peripheral program pc pll clock q3 q4 output cpu clock q1 q2 q3 q4 q1 q2 clock counter pc + 6 pc + 4 q1 q2 q3 q4 wake event note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. t ost (1) t pll (1) osts bit set pc + 2
pic18f6310/6410/8310/8410 ds39635a-page 44 preliminary ? 2004 microchip technology inc. 3.4.1 pri_idle mode this mode is unique among the three low-power idle modes, in that it does not disable the primary device clock. for timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to ?warm up? or transition from another oscillator. pri_idle mode is entered from pri_run mode by setting the idlen bit and executing a sleep instruc- tion. if the device is in another run mode, set idlen first, then clear the scs bits and execute sleep . although the cpu is disabled, the peripherals continue to be clocked from the primary clock source specified by the fosc3:fosc0 configuration bits. the osts bit remains set (see figure 3-7). when a wake event occurs, the cpu is clocked from the primary clock source. a delay of interval t csd is required between the wake event and when code execution starts. this is required to allow the cpu to become ready to execute instructions. after the wake-up, the osts bit remains set. the idlen and scs bits are not affected by the wake-up (see figure 3-8). figure 3-7: transition timing for entry to pri_idle mode figure 3-8: transition timing for wake from idle to run mode q1 peripheral program pc pc + 2 osc1 q3 q4 q1 cpu clock clock counter q2 osc1 peripheral program pc cpu clock q1 q3 q4 clock counter q2 wake event t csd
? 2004 microchip technology inc. preliminary ds39635a-page 45 pic18f6310/6410/8310/8410 3.4.2 sec_idle mode in sec_idle mode, the cpu is disabled, but the peripherals continue to be clocked from the timer1 oscillator. this mode is entered from sec_run by set- ting the idlen bit and executing a sleep instruction. if the device is in another run mode, set idlen first, then set scs1:scs0 to ? 01 ? and execute sleep . when the clock source is switched to the timer1 oscillator, the primary oscillator is shut down, the osts bit is cleared and the t1run bit is set. when a wake event occurs, the peripherals continue to be clocked from the timer1 oscillator. after an interval of t csd following the wake event, the cpu begins exe- cuting code being clocked by the timer1 oscillator. the idlen and scs bits are not affected by the wake-up; the timer1 oscillator continues to run (see figure 3-8). 3.4.3 rc_idle mode in rc_idle mode, the cpu is disabled, but the periph- erals continue to be clocked from the internal oscillator block using the intosc multiplexer. this mode allows for controllable power conservation during idle periods. from rc_run, this mode is entered by setting the idlen bit and executing a sleep instruction. if the device is in another run mode, first set idlen, then set the scs1 bit and execute sleep . although its value is ignored, it is recommended that scs0 also be cleared; this is to maintain software compatibility with future devices. the intosc multiplexer may be used to select a higher clock frequency by modifying the ircf bits before executing the sleep instruction. when the clock source is switched to the intosc multiplexer, the primary oscillator is shut down and the osts bit is cleared. if the ircf bits are set to any non-zero value, or the intsrc bit is set, the intosc output is enabled. the iofs bit becomes set after the intosc output becomes stable, after an interval of t iobst (parameter 39, table 26-12). clocks to the peripherals continue while the intosc source stabilizes. if the ircf bits were previously at a non-zero value, or intsrc was set before the sleep instruction was executed and the intosc source was already stable, the iofs bit will remain set. if the ircf bits and intsrc are all clear, the intosc output will not be enabled; the iofs bit will remain clear and there will be no indication of the current clock source. when a wake event occurs, the peripherals continue to be clocked from the intosc multiplexer. after a delay of t csd following the wake event, the cpu begins exe- cuting code, being clocked by the intosc multiplexer. the idlen and scs bits are not affected by the wake-up. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. note: the timer1 oscillator should already be running prior to entering sec_idle mode. if the t1oscen bit is not set when the sleep instruction is executed, the sleep instruction will be ignored and entry to sec_idle mode will not occur. if the timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. in such situations, initial oscillator operation is far from stable and unpredictable operation may result.
pic18f6310/6410/8310/8410 ds39635a-page 46 preliminary ? 2004 microchip technology inc. 3.5 exiting idle and sleep modes an exit from sleep mode or any of the idle modes is triggered by an interrupt, a reset or a wdt time-out. this section discusses the triggers that cause exits from power managed modes. the clocking subsystem actions are discussed in each of the power managed modes (see section 3.2 ?run modes? through section 3.4 ?idle modes? ). 3.5.1 exit by interrupt any of the available interrupt sources can cause the device to exit from an idle or sleep mode to a run mode. to enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the intcon or pie registers. the exit sequence is initiated when the corresponding interrupt flag bit is set. on all exits from idle or sleep modes by interrupt, code execution branches to the interrupt vector if the gie/gieh bit (intcon<7>) is set. otherwise, code execution continues or resumes without branching (see section 9.0 ?interrupts? ). a fixed delay of interval t csd , following the wake event, is required when leaving sleep and idle modes. this delay is required for the cpu to prepare for execution. instruction execution resumes on the first clock cycle following this delay. 3.5.2 exit by wdt time-out a wdt time-out will cause different actions depending on which power managed mode the device is in when the time-out occurs. if the device is not executing code (all idle modes and sleep mode), the time-out will result in an exit from the power managed mode (see section 3.2 ?run modes? and section 3.3 ?sleep mode? ). if the device is executing code (all run modes), the time-out will result in a wdt reset (see section 23.2 ?watchdog timer (wdt)? ). the wdt timer and postscaler are cleared by execut- ing a sleep or clrwdt instruction, losing a currently selected clock source (if the fail-safe clock monitor is enabled) and modifying the ircf bits in the osccon register if the internal oscillator block is the device clock source. 3.5.3 exit by reset normally, the device is held in reset by the oscillator start-up timer (ost) until the primary clock becomes ready. at that time, the osts bit is set and the device begins executing code. if the internal oscillator block is the new clock source, the iofs bit is set instead. the exit delay time from reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator if the new clock source is the primary clock. exit delays are summarized in table 3-2. code execution can begin before the primary clock becomes ready. if either the two-speed start-up (see section 23.3 ?two-speed start-up? ) or fail-safe clock monitor (see section 23.4 ?fail-safe clock monitor? ) is enabled, the device may begin execution as soon as the reset source has cleared. execution is clocked by the intosc multiplexer driven by the internal oscillator block. execution is clocked by the internal oscillator block until either the primary clock becomes ready, or a power managed mode is entered before the primary clock becomes ready; the primary clock is then shut down. 3.5.4 exit without an oscillator start-up delay certain exits from power managed modes do not invoke the ost at all. there are two cases: pri_idle mode, where the primary clock source is not stopped; and the primary clock source is not any of the lp, xt, hs or hspll modes. in these instances, the primary clock source either does not require an oscillator start-up delay since it is already running (pri_idle), or normally does not require an oscillator start-up delay (rc, ec and intio oscillator modes). however, a fixed delay of interval t csd , following the wake event, is still required when leaving sleep and idle modes to allow the cpu to prepare for execution. instruction execution resumes on the first clock cycle following this delay.
? 2004 microchip technology inc. preliminary ds39635a-page 47 pic18f6310/6410/8310/8410 table 3-2: exit delay on wake-up by reset from sleep mode or any idle mode (by clock sources) clock source before wake-up clock source after wake-up exit delay clock ready status bit (osccon) primary device clock (pri_idle mode) lp, xt, hs t csd (2) osts hspll ec, rc, intrc (1) ? intosc (3) iofs t1osc or intrc (1) lp, xt, hs t ost (4) osts hspll t ost + t rc (4) ec, rc, intrc (1) t csd (2) ? intosc (2) t iobst (5) iofs intosc (3) lp, xt, hs t ost (5) osts hspll t ost + t rc (4) ec, rc, intrc (1) t csd (2) ? intosc (2) none iofs none (sleep mode) lp, xt, hs t ost (4) osts hspll t ost + t rc (4) ec, rc, intrc (1) t csd (2) ? intosc (2) t iobst (5) iofs note 1: in this instance, refers specifically to the 31 khz intrc clock source. 2: t csd (parameter 38) is a required delay when waking from sleep and all idle modes and runs concurrently with any other required delays (see section 3.4 ?idle modes? ). 3: includes both the intosc 8 mhz source and postscaler derived frequencies. 4: t ost is the oscillator start-up timer (parameter 32). t rc is the pll lock-out timer (parameter f12); it is also designated as t pll . 5: execution continues during t iobst (parameter 39), the intosc stabilization period.
pic18f6310/6410/8310/8410 ds39635a-page 48 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 49 pic18f6310/6410/8310/8410 4.0 reset the pic18f6310/6410/8310/8410 devices differentiate between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during power managed modes d) watchdog timer (wdt) reset (during execution) e) programmable brown-out reset (bor) f) reset instruction g) stack full reset h) stack underflow reset this section discusses resets generated by mclr , por and bor and covers the operation of the various start-up timers. stack reset events are covered in section 5.1.3.4 ?stack full and underflow resets? . wdt resets are covered in section 23.2 ?watchdog timer (wdt)? . a simplified block diagram of the on-chip reset circuit is shown in figure 4-1. 4.1 rcon register device reset events are tracked through the rcon register (register 4-1). the lower five bits of the register indicate that a specific reset event has occurred. in most cases, these bits can only be set by the event and must be cleared by the application after the event. the state of these flag bits, taken together, can be read to indicate the type of reset that just occurred. this is described in more detail in section 4.6 ?reset state of registers? . the rcon register also has control bits for setting interrupt priority (ipen) and software control of the bor (sboren). interrupt priority is discussed in section 9.0 ?interrupts? . bor is covered in section 4.4 ?brown-out reset (bor)? . figure 4-1: simplified block diagram of on-chip reset circuit s r q external reset mclr v dd osc1 wdt time-out v dd rise detect ost/pwrt intrc (1) por pulse ost 10-bit ripple counter pwrt chip_reset 11-bit ripple counter enable ost (2) enable pwrt note 1: this is the intrc source from the inte rnal oscillator block and is separate from the rc oscillator of the clki pin. 2: see table 4-2 for time-out situations. brown-out reset boren reset instruction stack pointer stack full/underflow reset sleep ( )_idle 1024 cycles 65.5 ms 32 s mclre
pic18f6310/6410/8310/8410 ds39635a-page 50 preliminary ? 2004 microchip technology inc. register 4-1: rcon: reset control re gister r/w-0 r/w-1 (1) u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen sboren ?ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6 sboren: bor software enable bit if boren1:boren0 = 01 : 1 = bor is enabled 0 = bor is disabled if boren1:boren0 = 00 , 10 or 11 : bit is disabled and read as ? 0 ?. note 1: if sboren is enabled, its reset state is ? 1 ?; otherwise, it is ? 0 ?. bit 5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit 1 = the reset instruction was not executed (set by firmware only) 0 = the reset instruction was executed causing a device reset (must be set in software after a brown-out reset occurs) bit 3 to : watchdog timer time-out flag bit 1 = set by power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = set by power-up or by the clrwdt instruction 0 = set by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = a power-on reset has not occurred (set by firmware only) 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = a brown-out reset has not occurred (set by firmware only) 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note 1: it is recommended that the por bit be set after a power-on reset has been detected, so that subsequent power-on resets may be detected. 2: brown-out reset is said to have occurred when bor is ? 0 ? and por is ? 1 ? (assuming that por was set to ? 1 ? by software immediately after por).
? 2004 microchip technology inc. preliminary ds39635a-page 51 pic18f6310/6410/8310/8410 4.2 master clear (mclr ) the mclr pin provides a method for triggering a hard external reset of the device. a reset is generated by holding the pin low. pic18 extended mcu devices have a noise filter in the mclr reset path which detects and ignores small pulses. the mclr pin is not driven low by any internal resets, including the wdt. in pic18f6310/6410/8310/8410 devices, the mclr input can be disabled with the mclre configuration bit. when mclr is disabled, the pin becomes a digital input. see section 10.7 ?portg, trisg and latg registers? for more information. 4.3 power-on reset (por) a power-on reset pulse is generated on-chip whenever v dd rises above a certain threshold. this allows the device to start in the initialized state when v dd is adequate for operation. to take advantage of the por circuitry, tie the mclr pin through a resistor (1 k ? to 10 k ? ) to v dd . this will eliminate external rc components usually needed to create a power-on reset delay. a minimum rise rate for v dd is specified (parameter d004). for a slow rise time, see figure 4-2. when the device starts normal operation (i.e., exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. por events are captured by the por bit (rcon<1>). the state of the bit is set to ? 0 ? whenever a por occurs; it does not change for any other reset event. por is not reset to ? 1 ? by any hardware event. to capture multiple events, the user manually resets the bit to ? 1 ? in software following any por. figure 4-2: external power-on reset circuit (for slow v dd power-up) note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k ? is recommended to make sure that the voltage drop across r does not violate the device?s electrical specification. 3: r1 1 k ? will limit any current flowing into mclr from external capacitor c, in the event of mclr /v pp pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic18fxxxx v dd
pic18f6310/6410/8310/8410 ds39635a-page 52 preliminary ? 2004 microchip technology inc. 4.4 brown-out reset (bor) pic18f6310/6410/8310/8410 devices implement a bor circuit that provides the user with a number of configuration and power-saving options. the bor is controlled by the borv1:borv0 and boren1:boren0 configuration bits. there are a total of four bor configurations, which are summarized in table 4-1. the bor threshold is set by the borv1:borv0 bits. if bor is enabled (any values of boren1:boren0 except ? 00 ?), any drop of v dd below v bor (parameter d005) for greater than t bor (parameter 35) will reset the device. a reset may or may not occur if v dd falls below v bor for less than t bor . the chip will remain in brown-out reset until v dd rises above v bor . if the power-up timer is enabled, it will be invoked after v dd rises above v bor ; it then will keep the chip in reset for an additional time delay, t pwrt (parameter 33). if v dd drops below v bor while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises above v bor , the power-up timer will execute the additional time delay. bor and the power-up timer (pwrt) are independently configured. enabling the bor reset does not automatically enable the pwrt. 4.4.1 software enabled bor when boren1:boren0 = 01 , the bor can be enabled or disabled by the user in software. this is done with the control bit, sboren (rcon<6>). setting sboren enables the bor to function as previously described. clearing sboren disables the bor entirely. the sboren bit operates only in this mode; otherwise, it is read as ? 0 ?. placing the bor under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change the bor configuration. it also allows the user to tailor device power consumption in software by eliminating the incremental current that the bor consumes. while the bor current is typically very small, it may have some impact in low-power applications. 4.4.2 detecting bor when bor is enabled, the bor bit always resets to ? 0 ? on any bor or por event. this makes it difficult to determine if a bor event has occurred just by reading the state of bor alone. a more reliable method is to simultaneously check the state of both por and bor . this assumes that the por bit is reset to ? 1 ? in software immediately after any por event. if bor is ? 0 ? while por is ? 1 ?, it can be reliably assumed that a bor event has occurred. 4.4.3 disabling bor in sleep mode when boren1:boren0 = 10 , the bor remains under hardware control and operates as previously described. whenever the device enters sleep mode, however, the bor is automatically disabled. when the device returns to any other operating mode, bor is automatically re-enabled. this mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires bor protection the most. at the same time, it saves additional power in sleep mode by eliminating the small incremental bor current. table 4-1: bor configurations note: even when bor is under software control, the bor reset voltage level is still set by the borv1:borv0 configuration bits. it cannot be changed in software. bor configuration status of sboren (rcon<6>) bor operation boren1 boren0 00 unavailable bor is disabled; must be enabled by reprogramming the configuration bits. 01 available bor is enabled in software; operation controlled by sboren. 10 unavailable bor is enabled in hardware and active during the run and idle modes, disabled during sleep mode. 11 unavailable bor is enabled in hardware; must be disabled by reprogramming the configuration bits.
? 2004 microchip technology inc. preliminary ds39635a-page 53 pic18f6310/6410/8310/8410 4.5 device reset timers pic18f6310/6410/8310/8410 devices incorporate three separate on-chip timers that help regulate the power-on reset process. their main function is to ensure that the device clock is stable before code is executed. these timers are: power-up timer (pwrt) oscillator start-up timer (ost) pll lock time-out 4.5.1 power-up timer (pwrt) the power-up timer (pwrt) of the pic18f6310/6410/8310/8410 devices is an 11-bit counter which uses the intrc source as the clock input. this yields an approximate time interval of 2048 x 32 s = 65.6 ms. while the pwrt is counting, the device is held in reset. the power-up time delay depends on the intrc clock and will vary from chip to chip due to temperature and process variation. see dc parameter 33 for details. the pwrt is enabled by clearing the pwrten configuration bit. 4.5.2 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over (parameter 33). this ensures that the crystal oscillator or resonator has started and is stabilized. the ost time-out is invoked only for xt, lp, hs and hspll modes and only on power-on reset, or on exit from most power managed modes. 4.5.3 pll lock time-out with the pll enabled in its pll mode, the time-out sequence following a power-on reset is slightly different from other oscillator modes. a separate timer is used to provide a fixed time-out that is sufficient for the pll to lock to the main oscillator frequency. this pll lock time-out (t pll ) is typically 2 ms and follows the oscillator start-up time-out. 4.5.4 time-out sequence on power-up, the time-out sequence is as follows: 1. after the por pulse has cleared, pwrt time-out is invoked (if enabled). 2. then, the ost is activated. the total time-out will vary based on oscillator configuration and the status of the pwrt. figure 4-3, figure 4-4, figure 4-5, figure 4-6 and figure 4-7 all depict time-out sequences on power-up, with the power-up timer enabled and the device operating in hs oscillator mode. figures 4-3 through 4-6 also apply to devices operating in xt or lp modes. for devices in rc mode and with the pwrt disabled, on the other hand, there will be no time-out at all. since the time-outs occur from the por pulse, if mclr is kept low long enough, all time-outs will expire. bringing mclr high will begin execution immediately (figure 4-5). this is useful for testing purposes or to synchronize more than one pic18fxxxx device operating in parallel. table 4-2: time-out in various situations oscillator configuration power-up (2) and brown-out exit from power managed mode pwrten = 0 pwrten = 1 hspll 66 ms (1) + 1024 t osc + 2 ms (2) 1024 t osc + 2 ms (2) 1024 t osc + 2 ms (2) hs, xt, lp 66 ms (1) + 1024 t osc 1024 t osc 1024 t osc ec, ecio 66 ms (1) ?? rc, rcio 66 ms (1) ?? intio1, intio2 66 ms (1) ?? note 1: 66 ms (65.5 ms) is the nominal power-up timer (pwrt) delay. 2: 2 ms is the nominal time required for the pll to lock.
pic18f6310/6410/8310/8410 ds39635a-page 54 preliminary ? 2004 microchip technology inc. figure 4-3: time-out sequence on power-up (mclr tied to v dd , v dd rise < t pwrt ) figure 4-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 4-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
? 2004 microchip technology inc. preliminary ds39635a-page 55 pic18f6310/6410/8310/8410 figure 4-6: slow rise time (mclr tied to v dd , v dd rise > t pwrt ) figure 4-7: time-out sequence on por w/pll enabled (mclr tied to v dd ) v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset pll time-out t pll note: t ost = 1024 clock cycles. t pll 2 ms max. first three stages of the pwrt timer.
pic18f6310/6410/8310/8410 ds39635a-page 56 preliminary ? 2004 microchip technology inc. 4.6 reset state of registers most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. the other registers are forced to a ?reset state? depending on the type of reset that occurred. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of normal operation. status bits from the rcon register, ri , to , pd , por and bor, are set or cleared differently in different reset situations, as indicated in table 4-3. these bits are used in software to determine the nature of the reset. table 4-4 describes the reset states for all of the special function registers. these are categorized by power-on and brown-out resets, master clear and wdt resets and wdt wake-ups. table 4-3: status bits, their significance and the initialization condition for rcon register condition program counter rcon register stkptr register sboren ri to pd por bor stkful stkunf power-on reset 0000h 1 11100 0 0 reset instruction 0000h u (2) 0uuuu u u brown-out reset 0000h u (2) 111u0 u u mclr reset during power managed run modes 0000h u (2) u1uuu u u mclr reset during power managed idle modes and sleep 0000h u (2) u10uu u u wdt time-out during full power or power managed run modes 0000h u (2) u0uuu u u mclr reset during full power execution 0000h u (2) uuuuu u u stack full reset (stvren = 1 ) 0000h u (2) uuuuu 1 u stack underflow reset (stvren = 1 ) 0000h u (2) uuuuu u 1 stack underflow error (not an actual reset, stvren = 0 ) 0000h u (2) uuuuu u 1 wdt time-out during power managed idle or sleep modes pc + 2 u (2) u00uu u u interrupt exit from power managed modes pc + 2 (1) u (2) uu0uu u u legend: u = unchanged note 1: when the wake-up is due to an interrupt and the gieh or giel bits are set, the pc is loaded with the interrupt vector (008h or 0018h). 2: reset state is ? 1 ? for por and unchanged for all other resets when software bor is enabled (boren1:boren0 configuration bits = 01 and sboren = 1 ). otherwise, the reset state is ? 0 ?.
? 2004 microchip technology inc. preliminary ds39635a-page 57 pic18f6310/6410/8310/8410 table 4-4: initialization conditions for all registers register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt tosu 6x10 8x10 ---0 0000 ---0 0000 ---0 uuuu (3) tosh 6x10 8x10 0000 0000 0000 0000 uuuu uuuu (3) tosl 6x10 8x10 0000 0000 0000 0000 uuuu uuuu (3) stkptr 6x10 8x10 uu-0 0000 00-0 0000 uu-u uuuu (3) pclatu 6x10 8x10 ---0 0000 ---0 0000 ---u uuuu pclath 6x10 8x10 0000 0000 0000 0000 uuuu uuuu pcl 6x10 8x10 0000 0000 0000 0000 pc + 2 (2) tblptru 6x10 8x10 --00 0000 --00 0000 --uu uuuu tblptrh 6x10 8x10 0000 0000 0000 0000 uuuu uuuu tblptrl 6x10 8x10 0000 0000 0000 0000 uuuu uuuu tablat 6x10 8x10 0000 0000 0000 0000 uuuu uuuu prodh 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu prodl 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu intcon 6x10 8x10 0000 000x 0000 000u uuuu uuuu (1) intcon2 6x10 8x10 1111 1111 1111 1111 uuuu uuuu (1) intcon3 6x10 8x10 1100 0000 1100 0000 uuuu uuuu (1) indf0 6x10 8x10 n/a n/a n/a postinc0 6x10 8x10 n/a n/a n/a postdec0 6x10 8x10 n/a n/a n/a preinc0 6x10 8x10 n/a n/a n/a plusw0 6x10 8x10 n/a n/a n/a fsr0h 6x10 8x10 ---- xxxx ---- uuuu ---- uuuu fsr0l 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu wreg 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu indf1 6x10 8x10 n/a n/a n/a postinc1 6x10 8x10 n/a n/a n/a postdec1 6x10 8x10 n/a n/a n/a preinc1 6x10 8x10 n/a n/a n/a plusw1 6x10 8x10 n/a n/a n/a fsr1h 6x10 8x10 ---- xxxx ---- uuuu ---- uuuu fsr1l 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu bsr 6x10 8x10 ---- 0000 ---- 0000 ---- uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-3 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read ? 0 ?.
pic18f6310/6410/8310/8410 ds39635a-page 58 preliminary ? 2004 microchip technology inc. indf2 6x10 8x10 n/a n/a n/a postinc2 6x10 8x10 n/a n/a n/a postdec2 6x10 8x10 n/a n/a n/a preinc2 6x10 8x10 n/a n/a n/a plusw2 6x10 8x10 n/a n/a n/a fsr2h 6x10 8x10 ---- xxxx ---- uuuu ---- uuuu fsr2l 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu status 6x10 8x10 ---x xxxx ---u uuuu ---u uuuu tmr0h 6x10 8x10 0000 0000 0000 0000 uuuu uuuu tmr0l 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu t0con 6x10 8x10 1111 1111 1111 1111 uuuu uuuu osccon 6x10 8x10 0100 q000 0100 00q0 uuuu uuqu hlvdcon 6x10 8x10 --00 0101 --00 0101 --uu uuuu wdtcon 6x10 8x10 ---- ---0 ---- ---0 ---- ---u rcon (4) 6x10 8x10 0q-1 11q0 0q-q qquu uq-u qquu tmr1h 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu tmr1l 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu t1con 6x10 8x10 0000 0000 u0uu uuuu uuuu uuuu tmr2 6x10 8x10 0000 0000 0000 0000 uuuu uuuu pr2 6x10 8x10 1111 1111 1111 1111 1111 1111 t2con 6x10 8x10 -000 0000 -000 0000 -uuu uuuu sspbuf 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu sspadd 6x10 8x10 0000 0000 0000 0000 uuuu uuuu sspstat 6x10 8x10 0000 0000 0000 0000 uuuu uuuu sspcon1 6x10 8x10 0000 0000 0000 0000 uuuu uuuu sspcon2 6x10 8x10 0000 0000 0000 0000 uuuu uuuu adresh 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu adresl 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu adcon0 6x10 8x10 --00 0000 --00 0000 --uu uuuu adcon1 6x10 8x10 --00 0000 --00 0000 --uu uuuu adcon2 6x10 8x10 0-00 0000 0-00 0000 u-uu uuuu table 4-4: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-3 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read ? 0 ?.
? 2004 microchip technology inc. preliminary ds39635a-page 59 pic18f6310/6410/8310/8410 ccpr1h 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1l 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 6x10 8x10 --00 0000 --00 0000 --uu uuuu ccpr2h 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu ccpr2l 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 6x10 8x10 --00 0000 --00 0000 --uu uuuu ccpr3h 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu ccpr3l 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu ccp3con 6x10 8x10 --00 0000 --00 0000 --uu uuuu cvrcon 6x10 8x10 000- 0000 000- 0000 uuu- uuuu cmcon 6x10 8x10 0000 0111 0000 0111 uuuu uuuu tmr3h 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu tmr3l 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu t3con 6x10 8x10 0000 0000 uuuu uuuu uuuu uuuu pspcon 6x10 8x10 0000 ---- 0000 ---- uuuu ---- spbrg1 6x10 8x10 0000 0000 0000 0000 uuuu uuuu rcreg1 6x10 8x10 0000 0000 0000 0000 uuuu uuuu txreg1 6x10 8x10 0000 0000 0000 0000 uuuu uuuu txsta1 6x10 8x10 0000 0010 0000 0010 uuuu uuuu rcsta1 6x10 8x10 0000 000x 0000 000x uuuu uuuu ipr3 6x10 8x10 --11 ---1 --11 ---1 --uu ---u pir3 6x10 8x10 --00 ---0 --00 ---0 --uu ---u (1) pie3 6x10 8x10 --00 ---0 --00 ---0 --uu ---u ipr2 6x10 8x10 11-- 1111 11-- 1111 uu-- uuuu pir2 6x10 8x10 00-- 0000 00-- 0000 uu-- uuuu (1) pie2 6x10 8x10 00-- 0000 00-- 0000 uu-- uuuu ipr1 6x10 8x10 1111 1111 1111 1111 uuuu uuuu pir1 6x10 8x10 0000 0000 0000 0000 uuuu uuuu (1) pie1 6x10 8x10 0000 0000 0000 0000 uuuu uuuu memcon 6x10 8x10 0-00 --00 0-00 --00 u-uu --uu osctune 6x10 8x10 00-0 0000 00-0 0000 uu-u uuuu trisj 6x10 8x10 1111 1111 1111 1111 uuuu uuuu trish 6x10 8x10 1111 1111 1111 1111 uuuu uuuu table 4-4: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-3 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read ? 0 ?.
pic18f6310/6410/8310/8410 ds39635a-page 60 preliminary ? 2004 microchip technology inc. trisg 6x10 8x10 ---1 1111 ---1 1111 ---u uuuu trisf 6x10 8x10 1111 1111 1111 1111 uuuu uuuu trise 6x10 8x10 1111 1111 1111 1111 uuuu uuuu trisd 6x10 8x10 1111 1111 1111 1111 uuuu uuuu trisc 6x10 8x10 1111 1111 1111 1111 uuuu uuuu trisb 6x10 8x10 1111 1111 1111 1111 uuuu uuuu trisa (5) 6x10 8x10 1111 1111 (5) 1111 1111 (5) uuuu uuuu (5) latj 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu lath 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu latg 6x10 8x10 ---x xxxx ---u uuuu ---u uuuu latf 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu late 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu latd 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu latc 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu latb 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu lata (5) 6x10 8x10 xxxx xxxx (5) uuuu uuuu (5) uuuu uuuu (5) portj 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu porth 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu portg 6x10 8x10 --xx xxxx --uu uuuu --uu uuuu portf 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu porte 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu portd 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu portc 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu portb 6x10 8x10 xxxx xxxx uuuu uuuu uuuu uuuu porta (5) 6x10 8x10 xx0x 0000 (5) uu0u 0000 (5) uuuu uuuu (5) spbrgh1 6x10 8x10 0000 0000 0000 0000 uuuu uuuu baudcon1 6x10 8x10 01-0 0-00 01-0 0-00 uu-u u-uu spbrg2 6x10 8x10 0000 0000 0000 0000 uuuu uuuu rcreg2 6x10 8x10 0000 0000 0000 0000 uuuu uuuu txreg2 6x10 8x10 0000 0000 0000 0000 uuuu uuuu txsta2 6x10 8x10 0000 0010 0000 0010 uuuu uuuu rcsta2 6x10 8x10 0000 000x 0000 000x uuuu uuuu table 4-4: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-3 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read ? 0 ?.
? 2004 microchip technology inc. preliminary ds39635a-page 61 pic18f6310/6410/8310/8410 5.0 memory organization there are two types of memory in pic18 flash microcontroller devices: program memory data ram as harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. additional detailed information on the operation of the flash program memory is provided in section 6.0 ?program memory? . 5.1 program memory organization pic18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-mbyte program memory space. accessing a location between the upper boundary of the physically implemented memory and the 2-mbyte address will return all ? 0 ?s (a nop instruction). the pic18f6310 and pic18f8310 each have 8 kbytes of flash memory and can store up to 4,096 single-word instructions. the pic18f6410 and pic18f8410 each have 16 kbytes of flash memory and can store up to 8,192 single-word instructions. pic18 devices have two interrupt vectors. the reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. the program memory maps for the pic18f6310/6410/8310/8410 devices are shown in figure 5-1. figure 5-1: program memory map and stack for pic18f6310/6410/8310/8410 devices pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? call,rcall,return retfie,retlw 21 0000h 0018h on-chip program memory high priority interrupt vector 0008h user memory space 1fffffh 2000h 1fffh read ? 0 ? pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? call,rcall,return retfie,retlw 21 0000h 0018h on-chip program memory high priority interrupt vector 0008h user memory space 1fffffh 4000h 3fffh read ? 0 ? pic18fx310 pic18fx410
pic18f6310/6410/8310/8410 ds39635a-page 62 preliminary ? 2004 microchip technology inc. 5.1.1 pic18f8310/8410 program memory modes in addition to available on-chip flash program memory, 80-pin devices in this family can also address up to 2 mbytes of external program memory through an external memory interface. there are four distinct operating modes available to the controllers: microprocessor (mp) microprocessor with boot block (mpbb) extended microcontroller (emc) microcontroller (mc) the program memory mode is determined by setting the two least significant bits of the config3l config- uration byte, as shown in register 5-1. (see also section 23.1 ?configuration bits? for additional details on the device configuration bits.) the program memory modes operate as follows: the microcontroller mode accesses only on-chip flash memory. attempts to read above the physical limit of the on-chip flash (3fffh) causes a read of all ? 0 ?s (a nop instruction). the microcontroller mode is also the only operating mode available to pic18f6310 and pic18f6410 devices. the extended microcontroller mode allows access to both internal and external program memories as a single block. the device can access its entire on-chip flash memory; above this, the device accesses external program memory up to the 2-mbyte program space limit. as with boot block mode, execution automatically switches between the two memories as required. the microprocessor mode permits access only to external program memory; the contents of the on-chip flash memory is ignored. the 21-bit program counter permits access to the entire 2-mbyte linear program memory space. the microprocessor with boot block mode accesses on-chip flash memory from addresses 000000h to 0007ffh. above this, external program memory is accessed all the way up to the 2-mbyte limit. program execution automatically switches between the two memories as required. in all modes, the microcontroller has complete access to data ram. figure 5-2 compares the memory maps of the different program memory modes. the differences between on-chip and external memory access limitations are more fully explained in table 5-1. register 5-1: config3l: configuration byte register 3 low r/p-1 r/p-1 u-0 u-0 u-0 u-0 r/p-1 r/p-1 wait bw ? ? ? ?pm1pm0 bit 7 bit 0 bit 7 wait: external bus data wait enable bit 1 = wait selections unavailable, device will not wait 0 = wait programmed by wait1 and wait0 bits of memcom register (memcom<5:4>) bit 6 bw: external bus data width select bit 1 = 16-bit external bus data width 0 = 8-bit external bus data width bit 5-2 unimplemented: read as ? 0 ? bit 1-0 pm1:pm0: processor data memory mode select bits 11 = microcontroller mode 10 = microprocessor mode (1) 01 = microcontroller with boot block mode (1) 00 = extended microcontroller mode (1) note 1: this mode is available only on pic18f8410 devices. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value after erase ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39635a-page 63 pic18f6310/6410/8310/8410 figure 5-2: memory maps for pic18fx3 10/x410 program memory modes table 5-1: memory access for pic18f8310/8410 program memory modes 000000h 1fffffh external program memory external program memory on-chip program memory microcontroller mode (1) 000000h external on-chip on-chip program memory 1fffffh reads 000800h 1fffffh 0007ffh microprocessor with boot block mode (2) 000000h on-chip program memory external program memory memory flash on-chip program memory (no access) ? 0 ?s external on-chip memory flash on-chip flash external on-chip memory flash (top of memory) (top of memory) + 1 legend: (top of memory) represents upper boundary of on-chip pr ogram memory space (1fffh for pic18fx310, 3fffh for pic18fx410). shaded areas represent unimplement ed or inaccessible areas, depending on the mode. note 1: this mode is the only available mode on 64-pi n devices and the default on 80-pin devices. 2: these modes are only available on 80-pin devices. (no access) (top of memory) + 1 extended microcontroller mode (2) microprocessor mode (2) 000000h 1fffffh (top of memory) (top of memory) + 1 operating mode internal program memory external program memory execution from table read from table write to execution from table read from table write to microcontroller yes yes yes no access no access no access extended microcontroller yes yes yes yes yes yes microprocessor no access no access no access yes yes yes microprocessor w/ boot block yes yes yes yes yes yes
pic18f6310/6410/8310/8410 ds39635a-page 64 preliminary ? 2004 microchip technology inc. 5.1.2 program counter the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21 bits wide and is contained in three separate 8-bit registers. the low byte, known as the pcl register, is both readable and writable. the high byte, or pch register, contains the pc<15:8> bits; it is not directly readable or writable. updates to the pch register are performed through the pclath register. the upper byte is called pcu. this register contains the pc<20:16> bits; it is also not directly readable or writable. updates to the pcu register are performed through the pclatu register. the contents of pclath and pclatu are transferred to the program counter by any operation that writes pcl. similarly, the upper two bytes of the program counter are transferred to pclath and pclatu by an operation that reads pcl. this is useful for computed offsets to the pc (see section 5.1.5.1 ?computed goto? ). the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the least significant bit of pcl is fixed to a value of ? 0 ?. the pc increments by 2 to address sequential instructions in the program memory. the call, rcall, goto and program branch instructions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. 5.1.3 return address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc is pushed onto the stack when a call or rcall instruc- tion is executed, or an interrupt is acknowledged. the pc value is pulled off the stack on a return , retlw or a retfie instruction. pclatu and pclath are not affected by any of the return or call instructions. the stack operates as a 31-word by 21-bit ram and a 5-bit stack pointer register, stkptr. the stack space is not part of either program or data space. the stack pointer is readable and writable and the address on the top of the stack is readable and writable through the top-of-stack special file registers. data can also be pushed to or popped from the stack using these registers. a call type instruction causes a push onto the stack; the stack pointer is first incremented and the location pointed to by the stack pointer is written with the contents of the pc (already pointing to the instruction following the call ). a return type instruction causes a pop from the stack; the contents of the location pointed to by the stkptr are transferred to the pc and then the stack pointer is decremented. the stack pointer is initialized to ? 00000 ? after all resets. there is no ram associated with the location corresponding to a stack pointer value of ? 00000 ?; this is only a reset value. status bits indicate if the stack is full, has overflowed or has underflowed. 5.1.3.1 top-of-stack access only the top of the return address stack (tos) is readable and writable. a set of three registers, tosu:tosh:tosl, hold the contents of the stack location pointed to by the stkptr register (figure 5-3). this allows users to implement a software stack if necessary. after a call , rcall or interrupt, the software can read the pushed value by reading the tosu:tosh:tosl registers. these values can be placed on a user defined software stack. at return time, the software can return these values to tosu:tosh:tosl and do a return. the user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. figure 5-3: return address stack and associated registers 00011 001a34h 11111 11110 11101 00010 00001 00000 00010 return address stack <20:0> to p - o f - st a c k 000d58h tosl tosh tosu 34h 1ah 00h stkptr<4:0> top-of-stack registers stack pointer
? 2004 microchip technology inc. preliminary ds39635a-page 65 pic18f6310/6410/8310/8410 5.1.3.2 return stack pointer (stkptr) the stkptr register (register 5-2) contains the stack pointer value, the stkful (stack full) status bit and the stkunf (stack underflow) status bit. the value of the stack pointer can be 0 through 31. the stack pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. on reset, the stack pointer value will be zero. the user may read and write the stack pointer value. this feature can be used by a real-time operating system for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit is cleared by software or by a por. the action that takes place when the stack becomes full depends on the state of the stvren (stack overflow reset enable) configuration bit. (refer to section 23.1 ?configuration bits? for a description of the device configuration bits.) if stvren is set (default), the 31st push will push the (pc + 2) value onto the stack, set the stkful bit and reset the device. the stkful bit will remain set and the stack pointer will be set to zero. if stvren is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. any additional pushes will not overwrite the 31st push and stkptr will remain at 31. when the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the pc and sets the stkunf bit, while the stack pointer remains at zero. the stkunf bit will remain set until cleared by software, or until a por occurs. 5.1.3.3 push and pop instructions since the top-of-stack is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execu- tion, is a desirable feature. the pic18 instruction set includes two instructions, push and pop , that permit the tos to be manipulated under software control. tosu, tosh and tosl can be modified to place data or a return address on the stack. the push instruction places the current pc value onto the stack. this increments the stack pointer and loads the current pc value onto the stack. the pop instruction discards the current tos by decrementing the stack pointer. the previous value pushed onto the stack then becomes the tos value. register 5-2: stkptr: stack pointer register note: returning a value of zero to the pc on an underflow has the effect of vectoring the program to the reset vector where the stack conditions can be verified and appropriate actions can be taken. this is not the same as a reset, as the contents of the sfrs are not affected. r/c-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stkful stkunf ? sp4 sp3 sp2 sp1 sp0 bit 7 bit 0 bit 7 stkful: stack full flag bit (1) 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 stkunf: stack underflow flag bit (1) 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented: read as ? 0 ? bit 4-0 sp4:sp0: stack pointer location bits note 1: bit 7 and bit 6 are cleared by user software or by a por. legend: r = readable bit w = writable bit u = unimplemented c = clearable only bit -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 66 preliminary ? 2004 microchip technology inc. 5.1.3.4 stack full and underflow resets device resets on stack overflow and stack underflow conditions are enabled by setting the stvren bit in configuration register 4l. when stvren is set, a full or underflow condition will set the appropriate stkful or stkunf bit and then cause a device reset. when stvren is cleared, a full or underflow condition will set the appropriate stkful or stkunf bit, but not cause a device reset. the stkful or stkunf bits are cleared by the user software or a power-on reset. 5.1.4 fast register stack a fast register stack is provided for the status, wreg and bsr registers to provide a ?fast return? option for interrupts. this stack is only one level deep and is neither readable nor writable. it is loaded with the current value of the corresponding register when the processor vectors for an interrupt. all interrupt sources will push values into the stack registers. the values in the registers are then loaded back into the working registers if the retfie, fast instruction is used to return from the interrupt. if both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. if a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. in these cases, users must save the key registers in software during a low priority interrupt. if interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. if no interrupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a call label, fast instruction must be executed to save the status, wreg and bsr registers to the fast register stack. a return, fast instruction is then executed to restore these registers from the fast register stack. example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return. example 5-1: fast register stack code example 5.1.5 look-up tables in program memory there may be programming situations that require the creation of data structures, or look-up tables, in program memory. for pic18 devices, look-up tables can be implemented in two ways: computed goto table reads 5.1.5.1 computed goto a computed goto is accomplished by adding an offset to the program counter. an example is shown in example 5-2. a look-up table can be formed with an addwf pcl instruction and a group of retlw nn instructions. the w register is loaded with an offset into the table before executing a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruction executed will be one of the retlw nn instructions that returns the value ? nn ? to the calling function. the offset value (in wreg) specifies the number of bytes that the program counter should advance and should be multiples of 2 (lsb = 0 ). in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. example 5-2: computed goto using an offset value 5.1.5.2 table reads a better method of storing data in program memory allows two bytes of data to be stored in each instruction location. look-up table data may be stored two bytes per program word while programming. the table pointer (tblptr) register specifies the byte address and the table latch (tablat) register contains the data that is read from the program memory. data is transferred from program memory one byte at a time. table read operation is discussed further in section 6.1 ?table reads and table writes? . call sub1, fast ;status, wreg, bsr ;saved in fast register ;stack ? ? sub1 ? ? return fast ;restore values saved ;in fast register stack movf offset, w call table org nn00h table addwf pcl retlw nnh retlw nnh retlw nnh . . .
? 2004 microchip technology inc. preliminary ds39635a-page 67 pic18f6310/6410/8310/8410 5.2 pic18 instruction cycle 5.2.1 clocking scheme the microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (q1, q2, q3 and q4). internally, the program counter is incremented on every q1; the instruction is fetched from the program memory and latched into the instruc- tion register during q4. the instruction is decoded and executed during the following q1 through q4. the clocks and instruction execution flow are shown in figure 5-4. 5.2.2 instruction flow/pipelining an ?instruction cycle? consists of four q cycles, q1 through q4. the instruction fetch and execute are pipe- lined in such a manner that a fetch takes one instruc- tion cycle, while the decode and execute take another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction (example 5-3). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 5-4: clock/ instruction cycle example 5-3: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clko (rc mode) pc pc + 2 pc + 4 fetch inst (pc) execute inst (pc ? 2) fetch inst (pc + 2) execute inst (pc) fetch inst (pc + 4) execute inst (pc + 2) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ?flushed? from the pipeline, while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush ( nop ) 5. instruction @ address sub_1 fetch sub_1 execute sub_1
pic18f6310/6410/8310/8410 ds39635a-page 68 preliminary ? 2004 microchip technology inc. 5.2.3 instructions in program memory the program memory is addressed in bytes. instruc- tions are stored as two bytes or four bytes in program memory. the least significant byte of an instruction word is always stored in a program memory location with an even address (lsb = 0 ). to maintain alignment with instruction boundaries, the pc increments in steps of 2 and the lsb will always read ? 0 ? (see section 5.1.2 ?program counter? ). figure 5-5 shows an example of how instruction words are stored in the program memory. the call and goto instructions have the absolute program memory address embedded into the instruc- tion. since instructions are always stored on word boundaries, the data contained in the instruction is a word address. the word address is written to pc<20:1>, which accesses the desired byte address in program memory. instruction #2 in figure 5-5 shows how the instruction, goto 0006h , is encoded in the program memory. program branch instructions, which encode a relative address offset, operate in the same manner. the offset value stored in a br anch instruction represents the number of single-word instructions that the pc will be offset by. section 24.0 ?instruction set summary? provides further details of the instruction set. figure 5-5: instructions in program memory 5.2.4 two-word instructions the standard pic18 instruction set has four two-word instructions: call , movff , goto and lsfr . in all cases, the second word of the instructions always has ? 1111 ? as its four most significant bits; the other 12 bits are literal data, usually a data memory address. the use of ? 1111 ? in the 4 msbs of an instruction specifies a special form of nop . if the instruction is executed in proper sequence ? immediately after the first word ? the data in the second word is accessed and used by the instruction sequence. if the first word is skipped for some reason and the second word is executed by itself, a nop is executed instead. this is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the pc. example 5-4 shows how this works. example 5-4: two-word instructions word address lsb = 1 lsb = 0 program memory byte locations 000000h 000002h 000004h 000006h instruction 1: movlw 055h 0fh 55h 000008h instruction 2: goto 0006h efh 03h 00000ah f0h 00h 00000ch instruction 3: movff 123h, 456h c1h 23h 00000eh f4h 56h 000010h 000012h 000014h note: see section 5.5 ?program memory and the extended instruction set? for information on two-word instructions in the extended instruction set. case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, skip this word 1111 0100 0101 0110 ; execute this word as a nop 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 addwf reg3 ; continue code
? 2004 microchip technology inc. preliminary ds39635a-page 69 pic18f6310/6410/8310/8410 5.3 data memory organization the data memory in pic18 devices is implemented as static ram. each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. the memory space is divided into as many as 16 banks that contain 256 bytes each. pic18f6310/6410/8310/8410 devices implement only 3 complete banks, for a total of 768 bytes. figure 5-6 shows the data memory organization for the devices. the data memory contains special function registers (sfrs) and general purpose registers (gprs). the sfrs are used for control and status of the controller and peripheral functions, while gprs are used for data storage and scratchpad operations in the user?s application. any read of an unimplemented location will read as ? 0 ?s. the instruction set and architecture allow operations across all banks. the entire data memory may be accessed by direct, indirect or indexed addressing modes. addressing modes are discussed later in this section. to ensure that commonly used registers (sfrs and select gprs) can be accessed in a single cycle, pic18 devices implement an access bank. this is a 256-byte memory space that provides fast access to sfrs and the lower portion of gpr bank 0 without using the bsr. section 5.3.2 ?access bank? provides a detailed description of the access ram. 5.3.1 bank select register large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. ideally, this means that an entire address does not need to be provided for each read or write operation. for pic18 devices, this is accom- plished with a ram banking scheme. this divides the memory space into16 contiguous banks of 256 bytes. depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit bank pointer. most instructions in the pic18 instruction set make use of the bank pointer, known as the bank select register (bsr). this sfr holds the 4 most significant bits of a location?s address; the instruction itself includes the 8 least significant bits. only the four lower bits of the bsr are implemented (bsr3:bsr0). the upper four bits are unused; they will always read ? 0 ? and cannot be written to. the bsr can be loaded directly by using the movlb instruction. the value of the bsr indicates the bank in data memory; the 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank?s lower boundary. the relationship between the bsr?s value and the bank division in data memory is shown in figure 5-7. since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. for example, writing what should be program data to an 8-bit address of f9h while the bsr is 0fh will end up resetting the program counter. while any bank can be selected, only those banks that are actually implemented can be read or written to. writes to unimplemented banks are ignored, while reads from unimplemented banks will return ? 0 ?s. even so, the status register will still be affected as if the operation was successful. the data memory map in figure 5-6 indicates which banks are implemented. in the core pic18 instruction set, only the movff instruction fully specifies the 12-bit address of the source and target registers. this instruction ignores the bsr completely when it executes. all other instructions include only the low-order address as an operand and must use either the bsr or the access bank to locate their target registers. note: the operation of some aspects of data memory are changed when the pic18 extended instruction set is enabled. see section 5.6 ?data memory and the extended instruction set? for more information.
pic18f6310/6410/8310/8410 ds39635a-page 70 preliminary ? 2004 microchip technology inc. figure 5-6: data memory map for pic18f6310/6410/8310/8410 devices bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000 = 0001 = 1111 060h 05fh f40h fffh 00h 5fh 60h ffh access bank when a = 0 : the bsr is ignored and the access bank is used. the first 128 bytes are general purpose ram (from bank 0). the second 128 bytes are special function registers (from bank 15). when a = 1 : the bsr specifies the bank used by the instruction. f3fh f00h effh 1ffh 100h 0ffh 000h access ram ffh 00h ffh 00h ffh 00h gpr gpr sfr access ram high access ram low bank 2 = 0010 (sfrs) 2ffh 200h 300h bank 3 ffh 00h 00h gpr ffh = 0011 = 1110 unused read as 00h unused to
? 2004 microchip technology inc. preliminary ds39635a-page 71 pic18f6310/6410/8310/8410 figure 5-7: use of the bank select register (direct addressing) 5.3.2 access bank while the use of the bsr with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. otherwise, data may be read from or written to the wrong location. this can be disastrous if a gpr is the intended target of an operation but an sfr is written to instead. verifying and/or changing the bsr for each read or write to data memory can become very inefficient. to streamline access for the most commonly used data memory locations, the data memory is configured with an access bank, which allows users to access a mapped block of memory without specifying a bsr. the access bank consists of the first 96 bytes of memory (00h-5fh) in bank 0 and the last 160 bytes of memory (60h-ffh) in block 15. the lower half is known as the ?access ram? and is composed of gprs. this upper half is where the device?s sfrs are mapped. these two areas are mapped contiguously in the access bank and can be addressed in a linear fashion by an 8-bit address (figure 5-6). the access bank is used by core pic18 instructions that include the access ram bit (the ?a? parameter in the instruction). when ?a? is equal to ? 1 ?, the instruction uses the bsr and the 8-bit address included in the opcode for the data memory address. when ?a? is ? 0 ?, however, the instruction is forced to use the access bank address map; the current value of the bsr is ignored entirely. using this ?forced? addressing allows the instruction to operate on a data address in a single cycle without updating the bsr first. for 8-bit addresses of 80h and above, this means that users can evaluate and operate on sfrs more efficiently. the access ram below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. access ram also allows for faster and more code efficient context saving and switching of variables. the mapping of the access bank is slightly different when the extended instruction set is enabled (xinst configuration bit = 1 ). this is discussed in more detail in section 5.6.3 ?mapping the access bank in indexed literal offset mode? . 5.3.3 general purpose register file pic18 devices may have banked memory in the gpr area. this is data ram, which is available for use by all instructions. gprs start at the bottom of bank 0 (address 000h) and grow upwards towards the bottom of the sfr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. note 1: the access ram bit of the instruction can be used to force an override of the selected bank (bsr<3:0>) to the registers of the access bank. 2: the movff instruction embeds the entire 12-bit address in the instruction. data memory bank select (2) 7 0 from opcode (2) 0000 000h 100h 200h 300h f00h e00h fffh bank 0 bank 1 bank 2 bank 14 bank 15 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh bank 3 through bank 13 0010 11111111 7 0 bsr (1) 11111111
pic18f6310/6410/8310/8410 ds39635a-page 72 preliminary ? 2004 microchip technology inc. 5.3.4 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. sfrs start at the top of data memory (fffh) and extend downward to occupy more than the top half of bank 15 (f60h to fffh). a list of these registers is given in table 5-2 and table 5-3. the sfrs can be classified into two sets: those associated with the ?core? device functionality (alu, resets and interrupts) and those related to the peripheral functions. the reset and interrupt registers are described in their respective chapters, while the alu?s status register is described later in this section. registers related to the operation of the peripheral features are described in the chapter for that peripheral. the sfrs are typically distributed among the peripherals whose functions they control. unused sfr locations are unimplemented and read as ? 0 ?s. table 5-2: special function register map for pic18f6310/6410/8310/8410 devices address name address name address name address name address name fffh tosu fdfh indf2 (1) fbfh ccpr1h f9fh ipr1 f7fh spbrgh1 ffeh tosh fdeh postinc2 (1) fbeh ccpr1l f9eh pir1 f7eh baudcon1 ffdh tosl fddh postdec2 (1) fbdh ccp1con f9dh pie1 f7dh ? (2) ffch stkptr fdch preinc2 (1) fbch ccpr2h f9ch memcon (3) f7ch ? (2) ffbh pclatu fdbh plusw2 (1) fbbh ccpr2l f9bh osctune f7bh ? (2) ffah pclath fdah fsr2h fbah ccp2con f9ah trisj (3) f7ah ? (2) ff9h pcl fd9h fsr2l fb9h ccpr3h f99h trish (3) f79h ? (2) ff8h tblptru fd8h status fb8h ccpr3l f98h trisg f78h ? (2) ff7h tblptrh fd7h tmr0h fb7h ccp3con f97h trisf f77h ? (2) ff6h tblptrl fd6h tmr0l fb6h ? (2) f96h trise f76h ? (2) ff5h tablat fd5h t0con fb5h cvrcon f95h trisd f75h ? (2) ff4h prodh fd4h ? (2) fb4h cmcon f94h trisc f74h ? (2) ff3h prodl fd3h osccon fb3h tmr3h f93h trisb f73h ? (2) ff2h intcon fd2h hlvdcon fb2h tmr3l f92h trisa f72h ? (2) ff1h intcon2 fd1h wdtcon fb1h t3con f91h latj (3) f71h ? (2) ff0h intcon3 fd0h rcon fb0h pspcon f90h lath (3) f70h ? (2) fefh indf0 (1) fcfh tmr1h fafh spbrg1 f8fh latg f6fh spbrg2 feeh postinc0 (1) fceh tmr1l faeh rcreg1 f8eh latf f6eh rcreg2 fedh postdec0 (1) fcdh t1con fadh txreg1 f8dh late f6dh txreg2 fech preinc0 (1) fcch tmr2 fach txsta1 f8ch latd f6ch txsta2 febh plusw0 (1) fcbh pr2 fabh rcsta1 f8bh latc f6bh rcsta2 feah fsr0h fcah t2con faah ? (2) f8ah latb f6ah ? (2) fe9h fsr0l fc9h sspbuf fa9h ? (2) f89h lata f69h ? (2) fe8h wreg fc8h sspadd fa8h ? (2) f88h portj (3) f68h ? (2) fe7h indf1 (1) fc7h sspstat fa7h ? (2) f87h porth (3) f67h ? (2) fe6h postinc1 (1) fc6h sspcon1 fa6h ? (2) f86h portg f66h ? (2) fe5h postdec1 (1) fc5h sspcon2 fa5h ipr3 f85h portf f65h ? (2) fe4h preinc1 (1) fc4h adresh fa4h pir3 f84h porte f64h ? (2) fe3h plusw1 (1) fc3h adresl fa3h pie3 f83h portd f63h ? (2) fe2h fsr1h fc2h adcon0 fa2h ipr2 f82h portc f62h ? (2) fe1h fsr1l fc1h adcon1 fa1h pir2 f81h portb f61h ? (2) fe0h bsr fc0h adcon2 fa0h pie2 f80h porta f60h ? (2) note 1: this is not a physical register. 2: unimplemented registers are read as ? 0 ?. 3: this register is not available on 64-pin devices.
? 2004 microchip technology inc. preliminary ds39635a-page 73 pic18f6310/6410/8310/8410 table 5-3: register file summary (pic18f6310/6410/8310/8410) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: tosu ? ? ? top-of-stack upper byte (tos<20:16>) ---0 0000 57, 64 tosh top-of-stack high byte (tos<15:8>) 0000 0000 57, 64 tosl top-of-stack low byte (tos<7:0>) 0000 0000 57, 64 stkptr stkful (6) stkunf (6) ? return stack pointer 00-0 0000 57, 65 pclatu ? ? ? holding register for pc<20:16> ---0 0000 57, 64 pclath holding register for pc<15:8> 0000 0000 57, 64 pcl pc low byte (pc<7:0>) 0000 0000 57, 64 tblptru ? ? bit 21 program memory table pointer upper byte (tblptr<20:16>) --00 0000 57, 88 tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 57, 88 tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 57, 88 tablat program memory table latch 0000 0000 57, 88 prodh product register high byte xxxx xxxx 57, 99 prodl product register low byte xxxx xxxx 57, 99 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 57, 103 intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 1111 1111 57, 104 intcon3 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if 1100 0000 57, 105 indf0 uses contents of fsr0 to address data memory ? value of fsr0 not changed (not a physical register) n/a 57, 79 postinc0 uses contents of fsr0 to address data memory ? value of fsr0 post-incremented (not a physical register) n/a 57, 80 postdec0 uses contents of fsr0 to address data memory ? value of fsr0 post-decremented (not a physical register) n/a 57, 80 preinc0 uses contents of fsr0 to address data memory ? value of fsr0 pre-incremented (not a physical register) n/a 57, 80 plusw0 uses contents of fsr0 to address data memory ? value of fsr0 pre-incremented (not a physical register), value of fsr0 offset by w n/a 57, 80 fsr0h ? ? ? ? indirect data memory address pointer 0 high ---- xxxx 57, 79 fsr0l indirect data memory address pointer 0 low byte xxxx xxxx 57, 79 wreg working register xxxx xxxx 57 indf1 uses contents of fsr1 to address data memory ? value of fsr1 not changed (not a physical register) n/a 57, 79 postinc1 uses contents of fsr1 to address data memory ? value of fsr1 post-incremented (not a physical register) n/a 57, 80 postdec1 uses contents of fsr1 to address data memory ? value of fsr1 post-decremented (not a physical register) n/a 57, 80 preinc1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register) n/a 57, 80 plusw1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register), value of fsr1 offset by w n/a 57, 80 fsr1h ? ? ? ? indirect data memory address pointer 1 high ---- xxxx 57, 79 fsr1l indirect data memory address pointer 1 low byte xxxx xxxx 57, 79 bsr ? ? ? ? bank select register ---- 0000 57, 69 indf2 uses contents of fsr2 to address data memory ? value of fsr2 not changed (not a physical register) n/a 58, 79 postinc2 uses contents of fsr2 to address data memory ? value of fsr2 post-incremented (not a physical register) n/a 58, 80 postdec2 uses contents of fsr2 to address data memory ? value of fsr2 post-decremented (not a physical register) n/a 58, 80 preinc2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register) n/a 58, 80 plusw2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register), value of fsr2 offset by w n/a 58, 80 fsr2h ? ? ? ? indirect data memory address pointer 2 high ---- xxxx 58, 79 fsr2l indirect data memory address pointer 2 low byte xxxx xxxx 58, 79 status ? ? ?novzdcc ---x xxxx 58, 77 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. shaded locations are unimplemented, read as ? 0 ?. note 1: the sboren bit is only available when the boren1:boren0 configuration bits = 01 ; otherwise it is disabled and reads as ? 0 ?. see section 4.4 ?brown-out reset (bor)? . 2: these registers and/or bits are not implemented on 64-pin devices, read as ? 0 ?. 3: the pllen bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ? 0 ?. see section 2.6.4 ?pll in intosc modes? . 4: the rg5 bit is only available when master clear is disabled (mclre configuration bit = 0 ); otherwise, rg5 reads as ? 0 ?. this bit is read-only. 5: ra6/ra7 and their associated latch and direction bits are individually configured as port pins based on various primary oscilla tor modes. when disabled, these bits read as ? 0 ?. 6: stkful and stkunf bits are cleared by user software or by a por.
pic18f6310/6410/8310/8410 ds39635a-page 74 preliminary ? 2004 microchip technology inc. tmr0h timer0 register high byte 0000 0000 58, 145 tmr0l timer0 register low byte xxxx xxxx 58, 145 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 58, 143 osccon idlen ircf2 ircf1 ircf0 osts iofs scs1 scs0 0100 q000 36, 58 hlvdcon vdirmag ? irvst hlvden hlvdl3 hlvdl2 hlvdl1 hlvdl0 0-00 0101 58, 265 wdtcon ? ? ? ? ? ? ?swdten ---- ---0 58, 280 rcon ipen sboren (1) ?ri to pd por bor 0q-1 11q0 50, 58, 115 tmr1h timer1 register high byte xxxx xxxx 58, 151 tmr1l timer1 register low byte 0000 0000 58, 151 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 58, 147 tmr2 timer2 register 1111 1111 58, 154 pr2 timer2 period register -000 0000 58, 154 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 -000 0000 58, 153 sspbuf ssp receive buffer/transmit register 0000 0000 58, 170, 178 sspadd ssp address register in i 2 c? slave mode. ssp baud rate reload register in i 2 c master mode. 0000 0000 58, 178 sspstat smp cke d/a psr/w ua bf 0000 0000 58, 170, 179 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 58, 171, 180 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 58, 181 adresh a/d result register high byte xxxx xxxx 58, 254 adresl a/d result register low byte 0000 0000 58, 254 adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon --00 0000 58, 245 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 qqqq 58, 246 adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 0-00 0000 58, 247 ccpr1h capture/compare/pwm register 1 high byte xxxx xxxx 59, 160 ccpr1l capture/compare/pwm register 1 low byte xxxx xxxx 59, 160 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 59, 159 ccpr2h capture/compare/pwm register 2 high byte xxxx xxxx 59, 160 ccpr2l capture/compare/pwm register 2 low byte 0000 0000 59, 160 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 59, 159 ccpr3h capture/compare/pwm register 3 high byte xxxx xxxx 59, 160 ccpr3l capture/compare/pwm register 3 low byte 0000 0000 59, 160 ccp3con ? ? dc3b1 dc3b0 ccp3m3 ccp3m2 ccp3m1 ccp3m0 --00 0000 59, 159 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 0000 59, 261 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 59, 255 tmr3h timer3 register high byte 0000 0000 59, 157 tmr3l timer3 register low byte 0000 0000 59, 157 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 59, 155 pspcon ibf obf ibov pspmode ? ? ? ? 0000 ---- 59, 141 table 5-3: register file summary (pic18f6310/6410/8310/8410) (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. shaded locations are unimplemented, read as ? 0 ?. note 1: the sboren bit is only available when the boren1:boren0 configuration bits = 01 ; otherwise it is disabled and reads as ? 0 ?. see section 4.4 ?brown-out reset (bor)? . 2: these registers and/or bits are not implemented on 64-pin devices, read as ? 0 ?. 3: the pllen bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ? 0 ?. see section 2.6.4 ?pll in intosc modes? . 4: the rg5 bit is only available when master clear is disabled (mclre configuration bit = 0 ); otherwise, rg5 reads as ? 0 ?. this bit is read-only. 5: ra6/ra7 and their associated latch and direction bits are individually configured as port pins based on various primary oscilla tor modes. when disabled, these bits read as ? 0 ?. 6: stkful and stkunf bits are cleared by user software or by a por.
? 2004 microchip technology inc. preliminary ds39635a-page 75 pic18f6310/6410/8310/8410 spbrg1 eusart1 baud rate generator 0000 0000 59, 213 rcreg1 eusart1 receive register 0000 0000 59, 220 txreg1 eusart1 transmit register xxxx xxxx 59, 218 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d xxxx xxxx 59, 210 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 0000 0000 59, 211 ipr3 ? ? rc2ip tx2ip ? ? ? ccp3ip --00 ---1 59, 114 pir3 ? ?rc2iftx2if ? ? ? ccp3if --00 ---1 59, 108 pie3 ? ? rc2ie tx2ie ? ? ? ccp3ie --00 ---1 59, 111 ipr2 oscfip cmip ? ? bclip hlvdip tmr3ip ccp2ip 11-- 1111 59, 113 pir2 oscfif cmif ? ? bclif hlvdif tmr3if ccp2if 00-- 0000 59, 107 pie2 oscfie cmie ? ? bclie hlvdie tmr3ie ccp2ie 00-- 0000 59, 110 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 1111 1111 59, 112 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 0000 0000 59, 106 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 0000 0000 59, 109 memcon (2) ebdis ?wait1wait0 ? ?wm1wm0 0-00 --00 59, 89 osctune intsrc pllen (3) ? tun4 tun3 tun2 tun1 tun0 00-0 0000 33, 59 trisj (2) data direction control register for portj 1111 1111 59, 139 trish (2) data direction control register for porth 1111 1111 59, 137 trisg ? ? ? data direction control register for portg ---1 1111 60, 135 trisf data direction control register for portf 1111 1111 60, 133 trise data direction control register for porte 1111 1111 60, 131 trisd data direction control register for portd 1111 1111 60, 128 trisc data direction control register for portc 1111 1111 60, 125 trisb data direction control register for portb 1111 1111 60, 122 trisa trisa7 (5) trisa6 (5) data direction control register for porta 1111 1111 60, 119 latj (2) read portj data latch, write portj data latch xxxx xxxx 60, 139 lath (2) read porth data latch, write porth data latch xxxx xxxx 60, 137 latg ? ? ? read portg data latch, write portg data latch ---x xxxx 60, 135 latf read portf data latch, write portf data latch xxxx xxxx 60, 133 late read porte data latch, write porte data latch xxxx xxxx 60, 131 latd read portd data latch, write portd data latch xxxx xxxx 60, 128 latc read portc data latch, write portc data latch xxxx xxxx 60, 125 latb read portb data latch, write portb data latch xxxx xxxx 60, 122 lata lata7 (5) lata6 (5) read porta data latch, write porta data latch xxxx xxxx 60, 119 portj (2) read portj pins, write portj data latch xxxx xxxx 60, 139 porth (2) read porth pins, write porth data latch xxxx xxxx 60, 137 portg ? ?rg5 (4) read portg pins <4:0>, write portg data latch <4:0> --xx xxxx 60, 135 portf read portf pins, write portf data latch xxxx xxxx 60, 133 porte read porte pins, write porte data latch xxxx xxxx 60, 131 portd read portd pins, write portd data latch xxxx xxxx 60, 128 portc read portc pins, write portc data latch xxxx xxxx 60, 125 portb read portb pins, write portb data latch xxxx xxxx 60, 122 porta ra7 (5) ra6 (5) read porta pins, write porta data latch xx0x 0000 60, 119 table 5-3: register file summary (pic18f6310/6410/8310/8410) (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. shaded locations are unimplemented, read as ? 0 ?. note 1: the sboren bit is only available when the boren1:boren0 configuration bits = 01 ; otherwise it is disabled and reads as ? 0 ?. see section 4.4 ?brown-out reset (bor)? . 2: these registers and/or bits are not implemented on 64-pin devices, read as ? 0 ?. 3: the pllen bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ? 0 ?. see section 2.6.4 ?pll in intosc modes? . 4: the rg5 bit is only available when master clear is disabled (mclre configuration bit = 0 ); otherwise, rg5 reads as ? 0 ?. this bit is read-only. 5: ra6/ra7 and their associated latch and direction bits are individually configured as port pins based on various primary oscilla tor modes. when disabled, these bits read as ? 0 ?. 6: stkful and stkunf bits are cleared by user software or by a por.
pic18f6310/6410/8310/8410 ds39635a-page 76 preliminary ? 2004 microchip technology inc. spbrgh1 eusart1 baud rate generator high byte 0000 0000 60, 213 baudcon1 abdovf rcidl ? sckp brg16 ? wue abden 01-0 0-00 60, 212 spbrg2 ausart2 baud rate generator 0000 0000 60, 234 rcreg2 ausart2 receive register 0000 0000 60, 238 txreg2 ausart2 transmit register xxxx xxxx 60, 236 txsta2 csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 60, 232 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 0000 000x 60, 233 table 5-3: register file summary (pic18f6310/6410/8310/8410) (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. shaded locations are unimplemented, read as ? 0 ?. note 1: the sboren bit is only available when the boren1:boren0 configuration bits = 01 ; otherwise it is disabled and reads as ? 0 ?. see section 4.4 ?brown-out reset (bor)? . 2: these registers and/or bits are not implemented on 64-pin devices, read as ? 0 ?. 3: the pllen bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ? 0 ?. see section 2.6.4 ?pll in intosc modes? . 4: the rg5 bit is only available when master clear is disabled (mclre configuration bit = 0 ); otherwise, rg5 reads as ? 0 ?. this bit is read-only. 5: ra6/ra7 and their associated latch and direction bits are individually configured as port pins based on various primary oscilla tor modes. when disabled, these bits read as ? 0 ?. 6: stkful and stkunf bits are cleared by user software or by a por.
? 2004 microchip technology inc. preliminary ds39635a-page 77 pic18f6310/6410/8310/8410 5.3.5 status register the status register, shown in register 5-3, contains the arithmetic status of the alu. as with any other sfr, it can be the operand for any instruction. if the status register is the destination for an instruction that affects the z, dc, c, ov or n bits, the results of the instruction are not written; instead, the status is updated according to the instruction performed. there- fore, the result of an instruction with the status register as its destination may be different than intended. as an example, clrf status , will set the z bit and leave the remaining status bits unchanged (? 000u u1uu ?). it is recommended that only bcf , bsf , swapf , movff and movwf instructions are used to alter the status register, because these instructions do not affect the z, c, dc, ov or n bits in the status register. for other instructions that do not affect status bits, see the instruction set summaries in table 24-2 and table 24-3. register 5-3: status register note: the c and dc bits operate as a borrow and digit borrow bit, respectively, in subtraction. u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ?novzdcc bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4 n: negative bit this bit is used for signed arithmetic (2?s complement). it indicates whether the result was negative (alu msb = 1 ). 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (2?s complement). it indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit for addwf , addlw , sublw and subwf instructions: 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result note: for borrow, the polarity is reversed. a subtraction is executed by adding the 2?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. bit 0 c: carry/borrow bit for addwf , addlw , sublw and subwf instructions: 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow, the polarity is reversed. a subtraction is executed by adding the 2?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low-order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 78 preliminary ? 2004 microchip technology inc. 5.4 data addressing modes while the program memory can be addressed in only one way ? through the program counter ? information in the data memory space can be addressed in several ways. for most instructions, the addressing mode is fixed. other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. the addressing modes are: inherent literal direct indirect an additional addressing mode, indexed literal offset, is available when the extended instruction set is enabled (xinst configuration bit = 1 ). its operation is discussed in greater detail in section 5.6.1 ?indexed addressing with literal offset? . 5.4.1 inherent and literal addressing many pic18 control instructions do not need any argument at all; they either perform an operation that globally affects the device, or they operate implicitly on one register. this addressing mode is known as inherent addressing. examples include sleep , reset and daw . other instructions work in a similar way but require an additional explicit argument in the opcode. this is known as literal addressing mode, because they require some literal value as an argument. examples include addlw and movlw , which respectively, add or move a literal value to the w register. other examples include call and goto , which include a 20-bit program memory address. 5.4.2 direct addressing direct addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. the options are specified by the arguments accompanying the instruction. in the core pic18 instruction set, bit-oriented and byte-oriented instructions use some version of direct addressing by default. all of these instructions include some 8-bit literal address as their least significant byte. this address specifies either a register address in one of the banks of data ram ( section 5.3.3 ?general purpose register file? ), or a location in the access bank ( section 5.3.2 ?access bank? ) as the data source for the instruction. the access ram bit ?a? determines how the address is interpreted. when ?a? is ? 1 ?, the contents of the bsr ( section 5.3.1 ?bank select register? ) are used with the address to determine the complete 12-bit address of the register. when ?a? is ? 0 ?, the address is interpreted as being a register in the access bank. addressing that uses the access ram is sometimes also known as direct forced addressing mode. a few instructions, such as movff , include the entire 12-bit address (either source or destination) in their opcodes. in these cases, the bsr is ignored entirely. the destination of the operation?s results is determined by the destination bit ?d?. when ?d? is ? 1 ?, the results are stored back in the source register, overwriting its origi- nal contents. when ?d? is ? 0 ?, the results are stored in the w register. instructions without the ?d? argument have a destination that is implicit in the instruction; their destination is either the target register being operated on, or the w register. 5.4.3 indirect addressing indirect addressing allows the user to access a location in data memory without giving a fixed address in the instruction. this is done by using file select registers (fsrs) as pointers to the locations to be read or written to. since the fsrs are themselves located in ram as special file registers, they can also be directly manip- ulated under program control. this makes fsrs very useful in implementing data structures, such as tables and arrays in data memory. the registers for indirect addressing are also implemented with indirect file operands (indfs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. this allows for efficient code using loops, such as the example of clearing an entire ram bank in example 5-5. it also enables users to perform indexed addressing and other stack pointer operations for program memory in data memory. example 5-5: how to clear ram (bank 1) using indirect addressing note: the execution of some instructions in the core pic18 instruction set are changed when the pic18 extended instruction set is enabled. see section 5.6 ?data memory and the extended instruction set? for more information. lfsr fsr0, 100h ; next clrf postinc0 ; clear indf ; register then ; inc pointer btfss fsr0h, 1 ; all done with ; bank1? bra next ; no, clear next continue ; yes, continue
? 2004 microchip technology inc. preliminary ds39635a-page 79 pic18f6310/6410/8310/8410 5.4.3.1 fsr registers and the indf operand at the core of indirect addressing are three sets of registers: fsr0, fsr1 and fsr2. each represents a pair of 8-bit registers, fsrnh and fsrnl. the four upper bits of the fsrnh register are not used, so each fsr pair holds a 12-bit value. this represents a value that can address the entire range of the data memory in a linear fashion. the fsr register pairs, then, serve as pointers to data memory locations. indirect addressing is accomplished with a set of indirect file operands, indf0 through indf2. these can be thought of as ?virtual? registers: they are mapped in the sfr space but are not physically imple- mented. reading or writing to a particular indf register actually accesses its corresponding fsr register pair. a read from indf1, for example, reads the data at the address indicated by fsr1h:fsr1l. instructions that use the indf registers as operands actually use the contents of their corresponding fsr as a pointer to the instruction?s target. the indf operand is just a convenient way of using the pointer. because indirect addressing uses a full 12-bit address, data ram banking is not necessary. thus, the current contents of the bsr and the access ram bit have no effect on determining the target address. figure 5-8: indirect addressing fsr1h:fsr1l 0 7 data memory 000h 100h 200h 300h f00h e00h fffh bank 0 bank 1 bank 2 bank 14 bank 15 bank 3 through bank 13 addwf, indf1, 1 0 7 using an instruction with one of the indirect addressing registers as the operand.... ...uses the 12-bit address stored in the fsr pair associated with that register.... ...to determine the data memory location to be used in that operation. in this case, the fsr1 pair contains fcch. this means the contents of location fcch will be added to that of the w register and stored back in fcch. xxxx 1111 11001100
pic18f6310/6410/8310/8410 ds39635a-page 80 preliminary ? 2004 microchip technology inc. 5.4.3.2 fsr registers and postinc, postdec, preinc and plusw in addition to the indf operand, each fsr register pair also has four additional indirect operands. like indf, these are ?virtual? registers that cannot be indirectly read or written to. accessing these registers actually accesses the associated fsr register pair, but also performs a specific action on its stored value. they are: postdec: accesses the fsr value, then automatically decrements it by ? 1 ? afterwards postinc: accesses the fsr value, then automatically increments it by ? 1 ? afterwards preinc: increments the fsr value by ? 1 ?, then uses it in the operation plusw: adds the signed value of the w register (range of -127 to 128) to that of the fsr and uses the new value in the operation. in this context, accessing an indf register uses the value in the fsr registers without changing them. similarly, accessing a plusw register gives the fsr value offset by the value in the w register; neither value is actually changed in the operation. accessing the other virtual registers changes the value of the fsr registers. operations on the fsrs with postdec, postinc and preinc affect the entire register pair; that is, rollovers of the fsrnl register from ffh to 00h carry over to the fsrnh register. on the other hand, results of these operations do not change the value of any flags in the status register (e.g., z, n, ov, etc.). the plusw register can be used to implement a form of indexed addressing in the data memory space. by manipulating the value in the w register, users can reach addresses that are fixed offsets from pointer addresses. in some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 5.4.3.3 operations by fsrs on fsrs indirect addressing operations that target other fsrs or virtual registers represent special cases. for exam- ple, using an fsr to point to one of the virtual registers will not result in successful operations. as a specific case, assume that fsr0h:fsr0l contains fe7h, the address of indf1. attempts to read the value of the indf1, using indf0 as an operand, will return 00h. attempts to write to indf1, using indf0 as the operand, will result in a nop . on the other hand, using the virtual registers to write to an fsr pair may not occur as planned. in these cases, the value will be written to the fsr pair, but without any incrementing or decrementing. thus, writing to indf2 or postdec2 will write the same value to the fsr2h:fsr2l. since the fsrs are physical registers mapped in the sfr space, they can be manipulated through all direct operations. users should proceed cautiously when working on these registers, particularly if their code uses indirect addressing. similarly, operations by indirect addressing are gener- ally permitted on all other sfrs. users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device.
? 2004 microchip technology inc. preliminary ds39635a-page 81 pic18f6310/6410/8310/8410 5.5 program memory and the extended instruction set the operation of program memory is unaffected by the use of the extended instruction set. enabling the extended instruction set adds five additional two-word commands to the existing pic18 instruction set: addfsr , callw , movsf , movss and subfsr . these instructions are executed as described in section 5.2.4 ?two-word instructions? . 5.6 data memory and the extended instruction set enabling the pic18 extended instruction set (xinst configuration bit = 1 ) significantly changes certain aspects of data memory and its addressing. specifi- cally, the use of the access bank for many of the core pic18 instructions is different; this is due to the introduction of a new addressing mode for the data memory space. this mode also alters the behavior of indirect addressing using fsr2 and its associated operands. what does not change is just as important. the size of the data memory space is unchanged, as well as its linear addressing. the sfr map remains the same. core pic18 instructions can still operate in both direct and indirect addressing mode; inherent and literal instructions do not change at all. indirect addressing with fsr0 and fsr1 also remain unchanged. 5.6.1 indexed addressing with literal offset enabling the pic18 extended instruction set changes the behavior of indirect addressing using the fsr2 register pair and its associated file operands. under the proper conditions, instructions that use the access bank ? that is, most bit-oriented and byte-oriented instructions ? can invoke a form of indexed addressing using an offset specified in the instruction. this special addressing mode is known as indexed addressing with literal offset, or indexed literal offset mode. when using the extended instruction set, this addressing mode requires the following: the use of the access bank is forced (?a? = 0 ); and the file address argument is less than or equal to 5fh. under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the bsr in direct addressing), or as an 8-bit address in the access bank. instead, the value is interpreted as an offset value to an address pointer specified by fsr2. the offset and the contents of fsr2 are added to obtain the target address of the operation. 5.6.2 instructions affected by indexed literal offset mode any of the core pic18 instructions that can use direct addressing are potentially affected by the indexed literal offset addressing mode. this includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard pic18 instruction set. instruc- tions that only use inherent or literal addressing modes are unaffected. additionally, byte-oriented and bit-oriented instructions are not affected if they use the access bank (access ram bit is ? 1 ?), or include a file address of 60h or above. instructions meeting these criteria will continue to execute as before. a comparison of the different possi- ble addressing modes when the extended instruction set is enabled is shown in figure 5-9. those who desire to use byte-oriented or bit-oriented instructions in the indexed literal offset mode should note the changes to assembler syntax for this mode. this is described in more detail in section 24.2.1 ?extended instruction syntax? .
pic18f6310/6410/8310/8410 ds39635a-page 82 preliminary ? 2004 microchip technology inc. figure 5-9: comparing addressing options for bit-oriented and byte-oriented instructions (extended instruction set enabled) example instruction: addwf, f, d, a (opcode: 0010 01da ffff ffff ) when a = 0 and f 60h: the instruction executes in direct forced mode. ?f? is interpreted as a location in the access ram between 060h and fffh. this is the same as locations f60h to fffh (bank 15) of data memory. locations below 060h are not available in this addressing mode. when a = 0 and f 5fh: the instruction executes in indexed literal offset mode. ?f? is interpreted as an offset to the address value in fsr2. the two are added together to obtain the address of the target register for the instruction. the address can be anywhere in the data memory space. note that in this mode, the correct syntax is now: addwf [k], d where ?k? is the same as ?f?. when a = 1 (all values of f): the instruction executes in direct mode (also known as direct long mode). ?f? is interpreted as a location in one of the 16 banks of the data memory space. the bank is designated by the bank select register (bsr). the address can be in any implemented bank in the data memory space. 000h 060h 100h f00h f40h fffh valid range 00h 60h ffh data memory access ram bank 0 bank 1 through bank 14 bank 15 sfrs 000h 060h 100h f00h f40h fffh data memory bank 0 bank 1 through bank 14 bank 15 sfrs fsr2h fsr2l ffffffff 001001da ffffffff 001001da 000h 060h 100h f00h f40h fffh data memory bank 0 bank 1 through bank 14 bank 15 sfrs for ?f? bsr 00000000
? 2004 microchip technology inc. preliminary ds39635a-page 83 pic18f6310/6410/8310/8410 5.6.3 mapping the access bank in indexed literal offset mode the use of indexed literal offset addressing mode effectively changes how the lower part of access ram (00h to 5fh) is mapped. rather than containing just the contents of the bottom part of bank 0, this mode maps the contents from bank 0 and a user defined ?window? that can be located anywhere in the data memory space. the value of fsr2 establishes the lower bound- ary of the addresses mapped into the window, while the upper boundary is defined by fsr2 plus 95 (5fh). addresses in the access ram above 5fh are mapped as previously described (see section 5.3.2 ?access bank? ). an example of access bank remapping in this addressing mode is shown in figure 5-10. remapping of the access bank applies only to opera- tions using the indexed literal offset mode. operations that use the bsr (access ram bit is ? 1 ?) will continue to use direct addressing as before. any indirect or indexed operation that explicitly uses any of the indirect file operands (including fsr2) will continue to operate as standard indirect addressing. any instruction that uses the access bank, but includes a register address of greater than 05fh, will use direct addressing and the normal access bank map. 5.6.4 bsr in indexed literal offset mode although the access bank is remapped when the extended instruction set is enabled, the operation of the bsr remains unchanged. direct addressing, using the bsr to select the data memory bank, operates in the same manner as previously described. figure 5-10: remapping the access bank with indexed literal offset addressing data memory 000h 100h 200h f60h f00h fffh bank 1 bank 15 bank 2 through bank 14 sfrs 05fh addwf f, d, a fsr2h:fsr2l = 120h locations in the region from the fsr2 pointer (120h) to the pointer plus 05fh (17fh) are mapped to the bottom of the access ram (000h-05fh). special file registers at f60h through fffh are mapped to 60h through ffh, as usual. bank 0 addresses below 5fh are not available in this mode. they can still be addressed by using the bsr. access bank 00h ffh bank 0 sfrs bank 1 ?window? not accessible window example situation: 120h 17fh 5fh 60h
pic18f6310/6410/8310/8410 ds39635a-page 84 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 85 pic18f6310/6410/8310/8410 6.0 program memory for pic18fx310/x410 devices, the on-chip program memory is implemented as read-only memory. it is readable over the entire v dd range during normal operation; it cannot be written to or erased. reads from program memory are executed one byte at a time. pic18f8410 devices also implement the ability to read, write to and execute code from external memory devices using the external memory interface. in this implementation, external memory is used as all or part of the program memory space. the operation of the physical interface is discussed in section 7.0 ?external memory interface? . in all devices, a value written to the program memory space does not need to be a valid instruction. executing a program memory location that forms an invalid instruction results in a nop . 6.1 table reads and table writes to read and write to the program memory space, there are two operations that allow the processor to move bytes between the program memory space and the data ram: table read ( tblrd ) and table write ( tblwt ). the program memory space is 16 bits wide, while the data ram space is 8 bits wide. table reads and table writes move data between these two memory spaces through an 8-bit register (tablat). table read operations retrieve data from program memory and places it into the data ram space. table write operations place data from the data memory space on the external data bus. the actual process of writing the data to the particular memory device is determined by the requirements of the device itself. figure 6-1 shows the table operations as they relate to program memory and data ram. table operations work with byte entities. a table block containing data, rather than program instructions, is not required to be word-aligned. therefore, a table block can start and end at any byte address. if a table write is being used to write executable code into an external program memory, program instructions will need to be word-aligned. figure 6-1: table read and table write operations note: although it cannot be used in pic18f6310 devices in normal operation, the tblwt instruction is still implemented in the instruction set. executing the instruction takes two instruction cycles, but effectively results in a nop . the tblwt instruction is available in programming modes and is used during in-circuit serial programming (icsp). table pointer (1) table latch (8-bit) program memory space tblptrh tblptrl tablat tblptru instruction: tblrd* note 1: table pointer register points to a byte in the program memory space. 2: data is actually written to the memory location by the memory write algorithm. see section 6.4 ?writing to program memory space (pic18f8310/8410 only)? for more information. table pointer (1) table latch (8-bit) (2) tblptrh tblptrl tablat tblptru instruction: tblwt* program memory space data memory space data memory space
pic18f6310/6410/8310/8410 ds39635a-page 86 preliminary ? 2004 microchip technology inc. 6.2 control registers two control registers are used in conjunction with the tblrd and tblwt instructions: the tablat register and the tblptr register set. 6.2.1 tablat ? table latch register the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch register is used to hold 8-bit data during data transfers between the program memory space and data ram. 6.2.2 tblptr ? table pointer register the table pointer register (tblptr) addresses a byte within the program memory. it is comprised of three sfr registers: table pointer upper byte, table pointer high byte and table pointer low byte (tblptru:tblptrh:tblptrl). only the lower six bits of tblptru are used with tblptrh and tblptrl to form a 22-bit wide pointer. the contents of tblptr indicate a location in program memory space. the low-order 21 bits allow the device to address the full 2 mbytes of program memory space. the 22nd bit allows access to the configuration space, including the device id, user id locations and the configuration bits. the tblptr register set is updated when executing a tblrd or tblwt operation in one of four ways, based on the instruction?s arguments. these are detailed in table 6-1. these operations on the tblptr only affect the low-order 21 bits. when a tblrd or tblwt is executed, all 22 bits of the tblptr determine which address in the program memory space is to be read or written to. table 6-1: table pointer operations with tblrd and tblwt instructions 6.3 reading the flash program memory the tblrd instruction is used to retrieve data from the program memory space and places it into data ram. table reads from program memory are performed one byte at a time. tblptr points to a byte address in program space. executing tblrd places the byte pointed to into tablat. the internal program memory is typically organized by words. the least significant bit of the address selects between the high and low bytes of the word. figure 6-2 shows the interface between the internal program memory and the tablat. a typical method for reading data from program memory is shown in example 6-1. figure 6-2: reads from program memory example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+ tblwt*+ tblptr is incremented after the read/write tblrd*- tblwt*- tblptr is decremented after the read/write tblrd+* tblwt+* tblptr is incremented before the read/write (even byte address) program memory space (odd byte address) tblrd tablat tblptr = xxxxx1 fetch instruction register (ir) read register tblptr = xxxxx0
? 2004 microchip technology inc. preliminary ds39635a-page 87 pic18f6310/6410/8310/8410 example 6-1: reading a flash program memory word 6.4 writing to program memory space (pic18f8310/8410 only) the table write operation outputs the contents of the tblptr and tablat registers to the external address and data busses of the external memory interface. depending on the program memory mode selected, the operation may target any byte address in the device?s memory space. what happens to this data depends largely on the external memory device being used. for pic18 devices with enhanced flash memory, a single algorithm is used for writing to the on-chip program array. in the case of external devices, however, the algorithm is determined by the type of memory device and its requirements. in some cases, a specific instruction sequence must be sent before data can be written or erased. address and data demultiplexing, chip select operation and write time requirements must all be considered in creating the appropriate code. the connection of the data and address busses to the memory device are dictated by the interface being used, the data bus width and the target device. when using a 16-bit data path, the algorithm must take into account the width of the target memory. another important consideration is the write time requirement of the target device. if this is longer than the time that a tblwt operation makes data available on the interface, the algorithm must be adjusted to lengthen this time. it may be possible, for example, to buy enough time by increasing the length of the wait state on table operations. in all cases, it is important to remember that instruc- tions in the program memory space are word-aligned, with the least significant bit always being written to an even-numbered address (lsb = 0 ). if data is being stored in the program memory space, word alignment of the data is not required. a complete overview of interface algorithms is beyond the scope of this data sheet. the best place for timing and instruction sequence requirements is the data sheet of the memory device in question. for additional information on algorithm design for the external memory interface, refer to microchip application note an869, ?external memory interfacing techniques for the pic18f8xxx? (ds00869). 6.4.1 write verify depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 6.4.2 unexpected termination of write operation if a write is terminated by an unplanned event, such as loss of power or an unexpected reset, the memory location just programmed should be verified and repro- grammed if needed. if the application writes to external memory on a frequent basis, it may be necessary to implement an error trapping routine to handle these unplanned events. 6.5 erasing external memory (pic18f8310/8410 only) erasure is implemented in different ways on different devices. in many cases, it is possible to erase all or part of the memory by issuing a specific command. in some devices, it may be necessary to write ? 0 ?s to the locations to be erased. for specific information, consult the external memory device?s data sheet for clarification. 6.6 writing and erasing on-chip program memory (icsp mode) while the on-chip program memory is read-only in normal operating mode, it can be written to and erased as a function of in-circuit serial programming (icsp). in this mode, the tblwt operation is used in all devices to write to blocks of 64 bytes (32 words) at one time. write blocks are boundary-aligned with the code protection blocks. special commands are used to erase one or more code blocks of the progr am memory, or the entire device. movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the word movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl read_word tblrd*+ ; read into tablat and increment movf tablat, w ; get data movwf word_even tblrd*+ ; read into tablat and increment movfw tablat, w ; get data movf word_odd
pic18f6310/6410/8310/8410 ds39635a-page 88 preliminary ? 2004 microchip technology inc. the tblwt operation on write blocks is somewhat different than the word write operations for pic18f8310/8410 devices described here. a more complete description of block write operations is provided in the microchip document ?programming specifications for pic18fx410/x490 flash mcus? (ds39624). 6.7 flash program operation during code protection see section 23.5 ?program verification and code protection? for details on code protection of flash program memory. table 6-2: registers associated with flash program memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page tblptru ? ? bit 21 program memory table pointer upper byte (tblptr<20:16>) 57 tblptrh program memory table pointer high byte (tblptr<15:8>) 57 tblptrl program memory table pointer low byte (tblptr<7:0>) 57 tablat program memory table latch 57 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used during flash/eeprom access.
? 2004 microchip technology inc. preliminary ds39635a-page 89 pic18f6310/6410/8310/8410 7.0 external memory interface the external memory interface allows the device to access external memory devices (such as flash, eprom, sram, etc.) as program or data memory. it is implemented with 28 pins, multiplexed across four i/o ports. three ports (portd, porte and porth) are multiplexed with the address/data bus for a total of 20 available lines, while portj is multiplexed with the bus control signals. a list of the pins and their functions is provided in table 7-1. as implemented here, the interface is similar to that introduced on pic18f8x20 microcontrollers. the most notable difference is that the interface on pic18f8310/8410 devices supports both 16-bit and multiplexed 8-bit data width modes; it does not support the 8-bit demultiplexed mode. the bus width mode is set by the bw configuration bit when the device is programmed and cannot be changed in software. the operation of the interface is controlled by the memcon register (register 7-1). clearing the ebdis bit (memcon<7>) enables the interface and disables the i/o functions of the ports, as well as any other mul- tiplexed functions. setting the bit disables the interface and enables the ports. for a more complete discussion of the operating modes that use the external memory interface, refer to section 7.1 ?program memory modes and the external memory interface? . register 7-1: memcon: memory control register note: the external memory interface is not implemented on pic18f6310 and pic18f6410 (64-pin) devices. r/w-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 ebdis ?wait1wait0 ? ?wm1wm0 bit7 bit0 bit 7 ebdis : external bus disable bit 1 = external system bus disabled, all external bus drivers are mapped as i/o ports 0 = external system bus enabled, i/o ports are disabled bit 6 unimplemented : read as ? 0 ? bit 5-4 wait1:wait0: table reads and writes bus cycle wait count bits 11 = table reads and writes will wait 0 t cy 10 = table reads and writes will wait 1 t cy 01 = table reads and writes will wait 2 t cy 00 = table reads and writes will wait 3 t cy bit 3-2 unimplemented : read as ? 0 ? bit 1-0 wm1:wm0: tblwrt operation with 16-bit bus width bits 1x = word write mode: tablat0 and tablat1 word output, wrh active when tablat1 is written 01 = byte select mode: tablat data copied on both msb and lsb, wrh and (ub or lb ) will activate 00 = byte write mode: tablat data copied on both msb and lsb, wrh or wrl will activate legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 90 preliminary ? 2004 microchip technology inc. table 7-1: pic18f8310/8410 external bus ? i/o port functions 7.1 program memory modes and the external memory interface as previously noted, pic18f8310/8410 devices are capable of operating in any one of four program mem- ory modes, using combinations of on-chip and external program memory. the functions of the multiplexed port pins depends on the program memory mode selected, as well as the setting of the ebdis bit. in microcontroller mode, the bus is not active and the pins have their port functions only. writes to the memcom register are not permitted. in microprocessor mode , the external bus is always active and the port pins have only the external bus function. in microprocessor with boot block or extended microcontroller mode, the external program memory bus shares i/o port functions on the pins. when the device is fetching or doing table read/table write operations on the external program memory space, the pins will have the external bus function. if the device is fetching and accessing internal program memory locations only, the ebdis control bit will change the pins from external memory to i/o port functions. when ebdis = 0 , the pins function as the external bus. when ebdis = 1 , the pins function as i/o ports. if the device fetches or accesses external memory while ebdis = 1 , the pins will switch to external bus. if the ebdis bit is set by a progr am executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. at that time, the pins will change from external bus to i/o ports. when the device is executing out of internal memory (ebdis = 0 ) in microprocessor with boot block mode or extended microcontroller mode, the control signals will not be active. they will go to a state where the ad<15:0> and a<19:16> are tri-state; the ce , oe , wrh , wrl , ub and lb signals are ? 1 ?; ale and ba0 are ? 0 ?. name port bit function rd0/ad0/psp0 portd 0 input/output or system bus address bit 0 or data bit 0 or parallel slave port bit 0 rd1/ad1/psp1 portd 1 input/output or system bus address bit 1 or data bit 1 or parallel slave port bit 1 rd2/ad2/psp2 portd 2 input/output or system bus address bit 2 or data bit 2 or parallel slave port bit 2 rd3/ad3/psp3 portd 3 input/output or system bus address bit 3 or data bit 3 or parallel slave port bit 3 rd4/ad4/psp4 portd 4 input/output or system bus address bit 4 or data bit 4 or parallel slave port bit 4 rd5/ad5/psp5 portd 5 input/output or system bus address bit 5 or data bit 5 or parallel slave port bit 5 rd6/ad6/psp6 portd 6 input/output or system bus address bit 6 or data bit 6 or parallel slave port bit 6 rd7/ad7/psp7 portd 7 input/output or system bus address bit 7 or data bit 7 or parallel slave port bit 7 re0/ad8/rd porte 0 input/output or system bus address bit 8 or data bit 8 or parallel slave port read control pin re1/ad9/wr porte 1 input/output or system bus address bit 9 or data bit 9 or parallel slave port write control pin re2/ad10/cs porte 2 input/output or system bus address bit 10 or data bit 10 or parallel slave port chip select pin re3/ad11 porte 3 input/output or system bus address bit 11 or data bit 11 re4/ad12 porte 4 input/output or system bus address bit 12 or data bit 12 re5/ad13 porte 5 input/output or system bus address bit 13 or data bit 13 re6/ad14 porte 6 input/output or system bus address bit 14 or data bit 14 re7/ccp2 (1) /ad15 porte 7 input/output or capture 2 input/compare 2 output/pwm 2 output pin or system bus address bit 15 or data bit 15 rh0/ad16 porth 0 input/output or system bus address bit 16 rh1/ad17 porth 1 input/output or system bus address bit 17 rh2/ad18 porth 2 input/output or system bus address bit 18 rh3/ad19 porth 3 input/output or system bus address bit 19 rj0/ale portj 0 input/output or system bus address latch enable (ale) control pin rj1/oe portj 1 input/output or system bus output enable (oe ) control pin rj2/wrl portj 2 input/output or system bus write low (wrl ) control pin rj3/wrh portj 3 input/output or system bus write high (wrh ) control pin rj4/ba0 portj 4 input/output or system bus byte address bit 0 rj5/ce portj 5 input/output or system bus chip enable (ce ) control pin rj6/lb portj 6 input/output or system bus lower byte enable (lb ) control pin rj7/ub portj 7 input/output or system bus upper byte enable (ub ) control pin note 1: alternate assignment for ccp2 when ccp2mx configuration bit is cleared (all devices in microcontroller mode).
? 2004 microchip technology inc. preliminary ds39635a-page 91 pic18f6310/6410/8310/8410 7.2 16-bit mode in 16-bit mode, the external memory interface can be connected to external memories in three different configurations: 16-bit byte write 16-bit word write 16-bit byte select the configuration to be used is determined by the wm1:wm0 bits in the memcon register (memcon<1:0>). these three different configurations allow the designer maximum flexibility in using both 8-bit and 16-bit devices with 16-bit data. for all 16-bit modes, the address latch enable (ale) pin indicates that the address bits, a<15:0>, are avail- able on the external memory interface bus. following the address latch, the output enable signal (oe ) will enable both bytes of program memory at once to form a 16-bit instruction word. the chip enable signal (ce ) is active at any time that the microcontroller accesses external memory, whether reading or writing; it is inactive (asserted high) whenever the device is in sleep mode. in byte select mode, jedec standard flash memories will require ba0 for the byte address line and one i/o line to select between byte and word mode. the other 16-bit modes do not need ba0. jedec standard static ram memories will use the ub or lb signals for byte selection. 7.2.1 16-bit byte write mode figure 7-1 shows an example of 16-bit byte write mode for pic18f8310/8410 devices. this mode is used for two separate 8-bit memories connected for 16-bit operation. this generally includes basic eprom and flash devices. it allows table writes to byte-wide external memories. during a tblwt instruction cycle, the tablat data is presented on the upper and lower bytes of the ad15:ad0 bus. the appropriate wrh or wrl control line is strobed on the lsb of the tblptr. figure 7-1: 16-bit byte write mode example ad<7:0> a<19:16> ale d<15:8> 373 a d<7:0> a<19:0> a d<7:0> 373 oe wrh oe oe wr (1) wr (1) ce ce note 1: this signal only applies to table writes. see section 6.1 ?table reads and table writes? . wrl d<7:0> (lsb) (msb) pic18f8410 d<7:0> ad<15:8> address bus data bus control lines ce
pic18f6310/6410/8310/8410 ds39635a-page 92 preliminary ? 2004 microchip technology inc. 7.2.2 16-bit word write mode figure 7-2 shows an example of 16-bit word write mode for pic18f6410 devices. this mode is used for word-wide memories, which includes some of the eprom and flash type memories. this mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories. this method makes a distinction between tblwt cycles to even or odd addresses. during a tblwt cycle to an even address (tblptr<0> = 0 ), the tablat data is transferred to a holding latch and the external address data bus is tri-stated for the data portion of the bus cycle. no write signals are activated. during a tblwt cycle to an odd address (tblptr<0> = 1 ), the tablat data is presented on the upper byte of the ad15:ad0 bus. the contents of the holding latch are presented on the lower byte of the ad15:ad0 bus. the wrh signal is strobed for each write cycle; the wrl pin is unused. the signal on the ba0 pin indicates the lsb of tblptr, but it is left unconnected. instead, the ub and lb signals are active to select both bytes. the obvious limitation to this method is that the table write must be done in pairs on a specific word boundary to correctly write a word location. figure 7-2: 16-bit word write mode example ad<7:0> pic18f8410 ad<15:8> ale 373 a<20:1> 373 oe wrh a<19:16> a d<15:0> oe wr (1) ce d<15:0> jedec word eprom memory address bus data bus control lines note 1: this signal only applies to table writes. see section 6.1 ?table reads and table writes? . ce
? 2004 microchip technology inc. preliminary ds39635a-page 93 pic18f6310/6410/8310/8410 7.2.3 16-bit byte select mode figure 7-3 shows an example of 16-bit byte select mode. this mode allows table write operations to word-wide external memories with byte selection capability. this generally includes both word-wide flash and sram devices. during a tblwt cycle, the tablat data is presented on the upper and lower byte of the ad15:ad0 bus. the wrh signal is strobed for each write cycle; the wrl pin is not used. the ba0 or ub /lb signals are used to select the byte to be written, based on the least significant bit of the tblptr register. flash and sram devices use different control signal combinations to implement byte select mode. jedec standard flash memories require that a controller i/o port pin be connected to the memory?s byte/word pin to provide the select signal. they also use the ba0 signal from the controller as a byte address. jedec standard static ram memories, on the other hand, use the ub or lb signals to select the byte. figure 7-3: 16-bit byte select mode example ad<7:0> pic18f8410 ad<15:8> ale 373 a<20:1> 373 oe wrh a<19:16> wrl ba0 jedec word a d<15:0> a<20:1> ce d<15:0> i/o oe wr (1) a0 byte/word flash memory jedec word a d<15:0> ce d<15:0> oe wr (1) lb ub sram memory lb ub 138 (2) address bus data bus control lines note 1: this signal only applies to table writes. see section 6.1 ?table reads and table writes? . 2: demultiplexing is only required when mu ltiple memory devices are accessed.
pic18f6310/6410/8310/8410 ds39635a-page 94 preliminary ? 2004 microchip technology inc. 7.2.4 16-bit mode timing the presentation of control signals on the external memory bus is different for the various operating modes. typical signal timing diagrams are shown in figure 7-4 through figure 7-6. figure 7-4: external memory bus timi ng for tblrd (microprocessor mode) figure 7-5: external memory bus timing for tblrd (extended microcontroller mode) q2 q1 q3 q4 q2 q1 q3 q4 q4 q4 q4 q4 ale oe 3aabh wrh wrl ad<15:0> ba0 cf33h opcode fetch movlw 55h from 007556h 9256h 0e55h ? 1 ? ? 1 ? ? 1 ? ? 1 ? table read of 92h from 199e67h 1 t cy wait q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 apparent q actual q a<19:16> ce ? 0 ? ? 0 ? memory cycle instruction execution tblrd cycle 1 tblrd cycle 2 00h 0ch q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe ad<15:0> ce opcode fetch opcode fetch opcode fetch tblrd * tblrd cycle 1 addlw 55h from 000100h q2 q1 q3 q4 0ch cf33h tblrd 92h from 199e67h 9256h from 000104h memory cycle instruction execution inst(pc ? 2) tblrd cycle 2 movlw 55h from 000102h movlw
? 2004 microchip technology inc. preliminary ds39635a-page 95 pic18f6310/6410/8310/8410 figure 7-6: external memory bus timing for sleep (microprocessor mode) q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe 3aaah ad<15:0> 00h 00h ce opcode fetch opcode fetch sleep sleep from 007554h q1 bus inactive 0003h 3aabh 0e55h memory cycle instruction execution inst(pc ? 2) sleep mode, movlw 55h from 007556h
pic18f6310/6410/8310/8410 ds39635a-page 96 preliminary ? 2004 microchip technology inc. 7.3 8-bit mode the external memory interface implemented in pic18f6410 devices operates only in multiplexed 8-bit mode; data shares the 8 least significant bits of the address bus. figure 7-1 shows an example of 8-bit multiplexed mode for pic18f8310/8410 devices. this mode is used for a single 8-bit memory connected for 16-bit operation. the instructions will be fetched as two 8-bit bytes on a shared data/address bus. the two bytes are sequentially fetched within one instruction cycle (t cy ). therefore, the designer must choose external memory devices according to timing calculations based on 1/2 t cy (2 times the instruction rate). for proper memory speed selection, glue logic propagation delay times must be considered along with setup and hold times. the address latch enable (ale) pin indicates that the address bits a<15:0> are available on the external memory interface bus. the output enable signal (oe ) will enable one byte of program memory for a portion of the instruction cycle, then ba0 will change and the second byte will be enabled to form the 16-bit instruc- tion word. the least significant bit of the address, ba0, must be connected to the memory devices in this mode. the chip enable signal (ce ) is active at any time that the microcontroller accesses external memory, whether reading or writing; it is inactive (asserted high) whenever the device is in sleep mode. this generally includes basic eprom and flash devices. it allows table writes to byte-wide external memories. during a tblwt instruction cycle, the tablat data is presented on the upper and lower bytes of the ad15:ad0 bus. the appropriate level of the ba0 control line is strobed on the lsb of the tblptr. figure 7-7: 8-bit multiplexed mode example ad<7:0> a<19:16> ale d<15:8> 373 a<19:0> a d<7:0> oe oe wr (1) ce note 1: this signal only applies to table writes. see section 6.1 ?table reads and table writes? . wrl d<7:0> pic18f8410 ad<15:8> address bus data bus control lines ce a0 ba0
? 2004 microchip technology inc. preliminary ds39635a-page 97 pic18f6310/6410/8310/8410 7.3.1 8-bit mode timing the presentation of control signals on the external memory bus is different for the various operating modes. typical signal timing diagrams are shown in figure 7-4 through figure 7-6. figure 7-8: external memory bus timi ng for tblrd (microprocessor mode) figure 7-9: external memory bus timing for tblrd (extended microcontroller mode) q2 q1 q3 q4 q2 q1 q3 q4 q4 q4 q4 q4 ale oe abh wrl ad<7:0> ba0 33h opcode fetch movlw 55h from 007556h 92h 55h ? 1 ? ? 1 ? table read of 92h from 199e67h 1 t cy wait q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 apparent q actual q a<19:16> 0ch 00h ce ? 0 ? ? 0 ? memory cycle instruction execution tblrd cycle 1 tblrd cycle 2 3ah ad<15:8> cfh 0eh q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe ad<7:0> ce opcode fetch opcode fetch opcode fetch tblrd * tblrd cycle 1 addlw 55h from 000100h q2 q1 q3 q4 0ch 33h tblrd 92h from 199e67h 92h from 000104h memory cycle instruction execution inst(pc ? 2) tblrd cycle 2 movlw 55h from 000102h movlw ad<15:8> cfh
pic18f6310/6410/8310/8410 ds39635a-page 98 preliminary ? 2004 microchip technology inc. figure 7-10: external memory bus timing for sleep (microprocessor mode) q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe aah ad<7:0> 00h 00h ce opcode fetch opcode fetch sleep sleep from 007554h q1 bus inactive 00h abh 55h memory cycle instruction execution inst(pc ? 2) sleep mode, movlw 55h from 007556h ad<15:8> 3ah 3ah 03h 0eh
? 2004 microchip technology inc. preliminary ds39635a-page 99 pic18f6310/6410/8310/8410 8.0 8 x 8 hardware multiplier 8.1 introduction all pic18 devices include an 8 x 8 hardware multiplier as part of the alu. the multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair prodh:prodl. the multiplier?s operation does not affect any flags in the status register. making multiplication a hardware operation allows it to be completed in a single instruction cycle. this has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the pic18 devices to be used in many applica- tions previously reserved for digital signal processors. a comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in table 8-1. 8.2 operation example 8-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. only one instruction is required when one of the arguments is already loaded in the wreg register. example 8-2 shows the sequence to do an 8 x 8 signed multiplication. to account for the sign bits of the arguments, each argument?s most significant bit (msb) is tested and the appropriate subtractions are done. example 8-1: 8 x 8 unsigned multiply routine example 8-2: 8 x 8 signed multiply routine table 8-1: performance comparison for various multiply operations movf arg1, w ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movf arg1, w mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg1 movf arg2, w btfsc arg1, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg2 routine multiply method program memory (words) cycles (max) time @ 40 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 6.9 s27.6 s69 s hardware multiply 1 1 100 ns 400 ns 1 s 8 x 8 signed without hardware multiply 33 91 9.1 s36.4 s91 s hardware multiply 6 6 600 ns 2.4 s6 s 16 x 16 unsigned without hardware multiply 21 242 24.2 s96.8 s 242 s hardware multiply 28 28 2.8 s 11.2 s28 s 16 x 16 signed without hardware multiply 52 254 25.4 s 102.6 s 254 s hardware multiply 35 40 4.0 s16.0 s40 s
pic18f6310/6410/8310/8410 ds39635a-page 100 preliminary ? 2004 microchip technology inc. example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. equation 8-1 shows the algorithm that is used. the 32-bit result is stored in four registers (res3:res0). equation 8-1: 16 x 16 unsigned multiplication algorithm example 8-3: 16 x 16 unsigned multiply routine example 8-4 shows the sequence to do a 16 x 16 signed multiply. equation 8-2 shows the algorithm used. the 32-bit result is stored in four registers (res3:res0). to account for the sign bits of the arguments, the msb for each argument pair is tested and the appropriate subtractions are done. equation 8-2: 16 x 16 signed multiplication algorithm example 8-4: 16 x 16 signed multiply routine res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) movf arg1l, w mulwf arg2l ; arg1l * arg2l-> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h-> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h-> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l-> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; res3:res0= arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) + (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 ) + (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 ) movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; btfss arg2h, 7 ; arg2h:arg2l neg? bra sign_arg1 ; no, check arg1 movf arg1l, w ; subwf res2 ; movf arg1h, w ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? bra cont_code ; no, done movf arg2l, w ; subwf res2 ; movf arg2h, w ; subwfb res3 ; cont_code :
? 2004 microchip technology inc. preliminary ds39635a-page 101 pic18f6310/6410/8310/8410 9.0 interrupts the pic18f6310/6410/8310/8410 devices have multiple interrupt sources and an interrupt priority fea- ture that allows most interrupt sources to be assigned a high priority level or a low priority level. the high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. high priority interrupt events will interrupt any low priority interrupts that may be in progress. there are ten registers which are used to control interrupt operation. these registers are: rcon intcon intcon2 intcon3 pir1, pir2, pir3 pie1, pie2, pie3 ipr1, ipr2, ipr3 it is recommended that the microchip header files sup- plied with mplab ? ide be used for the symbolic bit names in these registers. this allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. in general, interrupt sources have three bits to control their operation. they are: flag bit to indicate that an interrupt event occurred enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set priority bit to select high priority or low priority the interrupt priority feature is enabled by setting the ipen bit (rcon<7>). when interrupt priority is enabled, there are two bits which enable interrupts globally. setting the gieh bit (intcon<7>) enables all interrupts that have the priority bit set (high priority). setting the giel bit (intcon<6>) enables all interrupts that have the priority bit cleared (low priority). when the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. individual interrupts can be disabled through their corresponding enable bits. when the ipen bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with picmicro ? mid-range devices. in compatibility mode, the interrupt priority bits for each source have no effect. intcon<6> is the peie bit, which enables/disables all peripheral interrupt sources. intcon<7> is the gie bit, which enables/disables all interrupt sources. all interrupts branch to address 0008h in compatibility mode. when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. if the ipen bit is cleared, this is the gie bit. if interrupt priority levels are used, this will be either the gieh or giel bit. high priority interrupt sources can interrupt a low priority interrupt. low priority interrupts are not processed while high priority interrupts are in progress. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (0008h or 0018h). once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. the ?return from interrupt? instruction, retfie , exits the interrupt routine and sets the gie bit (gieh or giel if priority levels are used), which re-enables interrupts. for external interrupt events, such as the int pins or the portb input change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one or two-cycle instructions. individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the gie bit. note: do not use the movff instruction to modify any of the interrupt control registers while any interrupt is enabled. doing so may cause erratic microcontroller behavior.
pic18f6310/6410/8310/8410 ds39635a-page 102 preliminary ? 2004 microchip technology inc. figure 9-1: pic18f6310/6410/8310/8410 interrupt logic tmr0ie gieh/gie giel/peie wake-up if in interrupt to cpu vector to location 0008h int2if int2ie int2ip int1if int1ie int1ip tmr0if tmr0ie tmr0ip rbif rbie rbip ipen tmr0if tmr0ip int1if int1ie int1ip int2if int2ie int2ip rbif rbie rbip int0if int0ie giel/peie interrupt to cpu vector to location ipen ipe 0018h pir1<7:0> pie1<7:0> ipr1<7:0> high priority interrupt generation low priority interrupt generation idle or sleep modes gieh/gie int3if int3ie int3ip int3if int3ie int3ip pir2<7:6, 3:0> pie2<7:6, 3:0> ipr2<7:6, 3:0> pir3<5:4, 0> pie3<5:4, 0> ipr3<5:4, 0> pir1<7:0> pie1<7:0> ipr1<7:0> pir2<7:6, 3:0> pie2<7:6, 3:0> ipr2<7:6, 3:0> pir3<5:4, 0> pie3<5:4, 0> ipr3<5:4, 0> ipen
? 2004 microchip technology inc. preliminary ds39635a-page 103 pic18f6310/6410/8310/8410 9.1 intcon registers the intcon registers are readable and writable registers which contain various enable, priority and flag bits. register 9-1: intcon: interrupt control register note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif bit 7 bit 0 bit 7 gie/gieh: global interrupt enable bit when ipen = 0 : 1 = enables all unmasked interrupts 0 = disables all interrupts when ipen = 1 : 1 = enables all high priority interrupts 0 = disables all interrupts bit 6 peie/giel: peripheral interrupt enable bit when ipen = 0 : 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts when ipen = 1 : 1 = enables all low priority peripheral interrupts 0 = disables all low priority peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt occurred (must be cleared in software) 0 = the int0 external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state note: a mismatch condition will continue to set this bit. reading portb will end the mismatch condition and allow the bit to be cleared. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 104 preliminary ? 2004 microchip technology inc. register 9-2: intcon2: interrupt control register 2 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg0 intedg1 intedg2 i ntedg3 tmr0ip int3ip rbip bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg0: external interrupt 0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5 intedg1: external interrupt 1 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 4 intedg2: external interrupt 2 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 3 intedg3: external interrupt 3 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 2 tmr0ip: tmr0 overflow interrupt priority bit 1 = high priority 0 = low priority bit 1 int3ip: int3 external interrupt priority bit 1 = high priority 0 = low priority bit 0 rbip: rb port change interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling.
? 2004 microchip technology inc. preliminary ds39635a-page 105 pic18f6310/6410/8310/8410 register 9-3: intcon3: interrupt control register 3 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if bit 7 bit 0 bit 7 int2ip: int2 external interrupt priority bit 1 = high priority 0 = low priority bit 6 int1ip: int1 external interrupt priority bit 1 = high priority 0 = low priority bit 5 int3ie: int3 external interrupt enable bit 1 = enables the int3 external interrupt 0 = disables the int3 external interrupt bit 4 int2ie: int2 external interrupt enable bit 1 = enables the int2 external interrupt 0 = disables the int2 external interrupt bit 3 int1ie: int1 external interrupt enable bit 1 = enables the int1 external interrupt 0 = disables the int1 external interrupt bit 2 int3if: int3 external interrupt flag bit 1 = the int3 external interrupt occurred (must be cleared in software) 0 = the int3 external interrupt did not occur bit 1 int2if: int2 external interrupt flag bit 1 = the int2 external interrupt occurred (must be cleared in software) 0 = the int2 external interrupt did not occur bit 0 int1if: int1 external interrupt flag bit 1 = the int1 external interrupt occurred (must be cleared in software) 0 = the int1 external interrupt did not occur legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling.
pic18f6310/6410/8310/8410 ds39635a-page 106 preliminary ? 2004 microchip technology inc. 9.2 pir registers the pir registers contain the individual flag bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt request (flag) registers (pir1, pir2, pir3). register 9-4: pir1: peripheral interrupt request (flag) register 1 note 1: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie (intcon<7>). 2: user software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if bit 7 bit 0 bit 7 pspif: parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6 adif: a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rc1if: eusart receive interrupt flag bit 1 = the eusart receive buffer, rcreg, is full (cleared when rcreg is read) 0 = the eusart receive buffer is empty bit 4 tx1if: eusart transmit interrupt flag bit 1 = the eusart transmit buffer, txreg, is empty (cleared when txreg is written) 0 = the eusart transmit buffer is full bit 3 sspif: master synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 ccp1if: ccp1 interrupt flag bit capture mode: 1 = a tmr1/tmr3 register capture occurred (must be cleared in software) 0 = no tmr1/tmr3 register capture occurred compare mode: 1 = a tmr1/tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1/tmr3 register compare match occurred pwm mode: unused in this mode. bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39635a-page 107 pic18f6310/6410/8310/8410 register 9-5: pir2: peripheral interrupt request (flag) register 2 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 oscfif cmif ? ? bclif hlvdif tmr3if ccp2if bit 7 bit 0 bit 7 oscfif: oscillator fail interrupt flag bit 1 = device oscillator failed, clock input has changed to intosc (must be cleared in software) 0 = device clock operating bit 6 cmif: comparator interrupt flag bit 1 = comparator input has changed (must be cleared in software) 0 = comparator input has not changed bit 5-4 unimplemented: read as ? 0 ? bit 3 bclif: bus collision interrupt flag bit 1 = a bus collision occurred (must be cleared in software) 0 = no bus collision occurred bit 2 hlvdif: high/low-voltage detect interrupt flag bit 1 = a low-voltage condition occurred (must be cleared in software) 0 = the device voltage is above the low-voltage detect trip point bit 1 tmr3if: tmr3 overflow interrupt flag bit 1 = tmr3 register overflowed (must be cleared in software) 0 = tmr3 register did not overflow bit 0 ccp2if: ccp2 interrupt flag bit capture mode: 1 = a tmr1/tmr3 register capture occurred (must be cleared in software) 0 = no tmr1/tmr3 register capture occurred compare mode: 1 = a tmr1/tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1/tmr3 register compare match occurred pwm mode: unused in this mode. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 108 preliminary ? 2004 microchip technology inc. register 9-6: pir3: peripheral interrupt request (flag) register 3 u-0 u-0 r-0 r-0 u-0 u-0 u-0 r/w-0 ? ? rc2if tx2if ? ? ? ccp3if bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 rc2if: ausart receive interrupt flag bit 1 = the ausart receive buffer, rcreg, is full (cleared when rcreg is read) 0 = the ausart receive buffer is empty bit 4 tx2if: ausart transmit interrupt flag bit 1 = the ausart transmit buffer, txreg, is empty (cleared when txreg is written) 0 = the ausart transmit buffer is full bit 3-1 unimplemented: read as ? 0 ? bit 0 ccp3if: ccp3 interrupt flag bit capture mode: 1 = a tmr1/tmr3 register capture occurred (must be cleared in software) 0 = no tmr1/tmr3 register capture occurred compare mode: 1 = a tmr1/tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1/tmr3 register compare match occurred pwm mode: unused in this mode. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39635a-page 109 pic18f6310/6410/8310/8410 9.3 pie registers the pie registers contain the individual enable bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt enable registers (pie1, pie2, pie3). when ipen = 0 , the peie bit must be set to enable any of these peripheral interrupts. register 9-7: pie1: peripheral interrupt enable register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 bit 7 pspie: parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6 adie: a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5 rc1ie: eusart receive interrupt enable bit 1 = enables the eusart receive interrupt 0 = disables the eusart receive interrupt bit 4 tx1ie: eusart transmit interrupt enable bit 1 = enables the eusart transmit interrupt 0 = disables the eusart transmit interrupt bit 3 sspie: master synchronous serial port interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 ccp1ie: ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie: tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 110 preliminary ? 2004 microchip technology inc. register 9-8: pie2: peripheral interrupt enable register 2 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 oscfie cmie ? ? bclie hlvdie tmr3ie ccp2ie bit 7 bit 0 bit 7 oscfie: oscillator fail interrupt enable bit 1 = enabled 0 =disabled bit 6 cmie: comparator interrupt enable bit 1 = enabled 0 =disabled bit 5-4 unimplemented: read as ? 0 ? bit 3 bclie: bus collision interrupt enable bit 1 = enabled 0 =disabled bit 2 hlvdie: high/low-voltage detect interrupt enable bit 1 = enabled 0 =disabled bit 1 tmr3ie: tmr3 overflow interrupt enable bit 1 = enabled 0 =disabled bit 0 ccp2ie: ccp2 interrupt enable bit 1 = enabled 0 =disabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39635a-page 111 pic18f6310/6410/8310/8410 register 9-9: pie3: peripheral interrupt enable register 3 u-0 u-0 r-0 r-0 u-0 u-0 u-0 r/w-0 ? ? rc2ie tx2ie ? ? ?ccp3ie bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 rc2ie: ausart receive interrupt enable bit 1 = enabled 0 = disabled bit 4 tx2ie: ausart transmit interrupt enable bit 1 = enabled 0 = disabled bit 3-1 unimplemented: read as ? 0 ? bit 0 ccp3ie: ccp3 interrupt enable bit 1 = enabled 0 = disabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 112 preliminary ? 2004 microchip technology inc. 9.4 ipr registers the ipr registers contain the individual priority bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt priority registers (ipr1, ipr2, ipr3). using the priority bits requires that the interrupt priority enable (ipen) bit be set. register 9-10: ipr1: peripheral interrupt priority register 1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip bit 7 bit 0 bit 7 pspip: parallel slave port read/write interrupt priority bit 1 =high priority 0 = low priority bit 6 adip: a/d converter interrupt priority bit 1 =high priority 0 = low priority bit 5 rc1ip: eusart receive interrupt priority bit 1 =high priority 0 = low priority bit 4 tx1ip: eusart transmit interrupt priority bit 1 =high priority 0 = low priority bit 3 sspip: master synchronous serial port interrupt priority bit 1 =high priority 0 = low priority bit 2 ccp1ip: ccp1 interrupt priority bit 1 =high priority 0 = low priority bit 1 tmr2ip: tmr2 to pr2 match interrupt priority bit 1 =high priority 0 = low priority bit 0 tmr1ip: tmr1 overflow interrupt priority bit 1 =high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39635a-page 113 pic18f6310/6410/8310/8410 register 9-11: ipr2: peripheral interrupt priority register 2 r/w-1 r/w-1 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 oscfip cmip ? ? bclip hlvdip tmr3ip ccp2ip bit 7 bit 0 bit 7 oscfip: oscillator fail interrupt priority bit 1 =high priority 0 = low priority bit 6 cmip: comparator interrupt priority bit 1 =high priority 0 = low priority bit 5-4 unimplemented: read as ? 0 ? bit 3 bclip: bus collision interrupt priority bit 1 =high priority 0 = low priority bit 2 hlvdip: high/low-voltage detect interrupt priority bit 1 =high priority 0 = low priority bit 1 tmr3ip: tmr3 overflow interrupt priority bit 1 =high priority 0 = low priority bit 0 ccp2ip: ccp2 interrupt priority bit 1 =high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 114 preliminary ? 2004 microchip technology inc. register 9-12: ipr3: peripheral interrupt priority register 3 u-0 u-0 r-0 r-0 u-0 u-0 u-0 r/w-1 ? ? rc2ip tx2ip ? ? ?ccp3ip bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 rc2ip: ausart receive priority flag bit 1 = high priority 0 = low priority bit 4 tx2ip: ausart transmit interrupt priority bit 1 = high priority 0 = low priority bit 3-1 unimplemented: read as ? 0 ? bit 0 ccp3ip: ccp3 interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39635a-page 115 pic18f6310/6410/8310/8410 9.5 rcon register the rcon register contains bits used to determine the cause of the last reset or wake-up from idle or sleep modes. rcon also contains the bit that enables interrupt priorities (ipen). register 9-13: rcon register r/w-0 r/w-1 u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen sboren ?ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6 sboren: software bor enable bit for details of bit operation and reset state, see register 4-1. bit 5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit for details of bit operation, see register 4-1. bit 3 to : watchdog timer time-out flag bit for details of bit operation, see register 4-1. bit 2 pd : power-down detection flag bit for details of bit operation, see register 4-1. bit 1 por : power-on reset status bit for details of bit operation, see register 4-1. bit 0 bor : brown-out reset status bit for details of bit operation, see register 4-1. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 116 preliminary ? 2004 microchip technology inc. 9.6 intn pin interrupts external interrupts on the rb0/int0, rb1/int1, rb2/ int2 and rb3/int3 pins are edge-triggered. if the corresponding intedgx bit in the intcon2 register is set (= 1 ), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. when a valid edge appears on the rbx/intx pin, the corresponding flag bit, intxf, is set. this interrupt can be disabled by clearing the corresponding enable bit, intxe. flag bit, intxf, must be cleared in software in the interrupt service routine before re-enabling the interrupt. all external interrupts (int0, int1, int2 and int3) can wake-up the processor from the power managed modes if bit intxe was set prior to going into power managed modes. if the global interrupt enable bit, gie, is set, the processor will branch to the interrupt vector following wake-up. interrupt priority for int1, int2 and int3 is determined by the value contained in the interrupt priority bits, int1ip (intcon3<6>), int2ip (intcon3<7>) and int3ip (intcon2<1>). there is no priority bit associated with int0. it is always a high priority interrupt source. 9.7 tmr0 interrupt in 8-bit mode (which is the default), an overflow in the tmr0 register (ffh 00h) will set flag bit, tmr0if. in 16-bit mode, an overflow in the tmr0h:tmr0l register pair (ffffh 0000h) will set tmr0if. the interrupt can be enabled/disabled by setting/clearing enable bit, tmr0ie (intcon<5>). interr upt priority for timer0 is determined by the value contained in the interrupt prior- ity bit, tmr0ip (intcon2<2>). see section 11.0 ?timer0 module? for further details on the timer0 module. 9.8 portb interrupt-on-change an input change on portb<7:4> sets flag bit, rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit, rbie (intcon<3>). interrupt priority for portb interrupt-on-change is determined by the value contained in the interrupt priority bit, rbip (intcon2<0>). 9.9 context saving during interrupts during interrupts, the return pc address is saved on the stack. additionally, the wreg, status and bsr registers are saved on the fast return stack. if a fast return from interrupt is not used (see section 5.3 ?data memory organization? ), the user may need to save the wreg, status and bsr registers on entry to the interrupt service routine. depending on the user?s application, other registers may also need to be saved. example 9-1 saves and restores the wreg, status and bsr registers during an interrupt service routine. example 9-1: saving status, wreg and bsr registers in ram movwf w_temp ; w_temp is in virtual bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr_tmep located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status
? 2004 microchip technology inc. preliminary ds39635a-page 117 pic18f6310/6410/8310/8410 10.0 i/o ports depending on the device selected and features enabled, there are up to nine ports available. some pins of the i/o ports are multiplexed with an alternate function from the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. each port has three registers for its operation. these registers are: tris register (data direction register) port register (reads the levels on the pins of the device) lat register (output latch) the data latch (lat register) is useful for read-modify-write operations on the value that the i/o pins are driving. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 10-1. figure 10-1: generic i/o port operation 10.1 porta, trisa and lata registers porta is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisa. setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins, whereas writing to it, will write to the port latch. the data latch register (lata) is also memory mapped. read-modify-write operations on the lata register read and write the latched output value for porta. the ra4 pin is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. pins ra6 and ra7 are multiplexed with the main oscillator pins; they are enabled as oscillator or i/o pins by the selec- tion of the main oscillator in the configuration register (see section 23.1 ?configuration bits? for details). when they are not used as port pins, ra6 and ra7 and their associated tris and lat bits are read as ? 0 ?. the other porta pins are multiplexed with the analog v ref + and v ref - inputs. the operation of pins ra5:ra0 as a/d converter inputs is selected by clearing or setting the pcfg3:pcfg0 control bits in the adcon1 register. the ra4/t0cki pin is a schmitt trigger input and an open-drain output. all other porta pins have ttl input levels and full cmos output drivers. the trisa register controls the direction of the porta pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 10-1: initializing porta data bus wr lat wr tris rd port data latch tris latch rd tris input buffer i/o pin (1) q d ck q d ck en qd en rd lat or port note 1: i/o pins have diode protection to v dd and v ss . note: on a power-on reset, ra5 and ra3:ra0 are configured as analog inputs and read as ? 0 ?. ra4 is configured as a digital input. clrf porta ; initialize porta by ; clearing output ; data latches clrf lata ; alternate method ; to clear output ; data latches movlw 07h ; configure a/d movwf adcon1 ; for digital inputs movwf 07h ; configure comparators movwf cmcon ; for digital input movlw 0cfh ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs
pic18f6310/6410/8310/8410 ds39635a-page 118 preliminary ? 2004 microchip technology inc. table 10-1: porta functions pin name function tris setting i/o i/o type description ra0/an0 ra0 0 o dig lata<0> data output; not affected by analog input. 1 i ttl porta<0> data input; disabled when analog input enabled. an0 1 i ana a/d input channel 0. default input configuration on por; does not affect digital output. ra1/an1 ra1 0 o dig lata<1> data output; not affected by analog input. 1 i ttl porta<1> data input; disabled when analog input enabled. an1 1 i ana a/d input channel 1. default input configuration on por; does not affect digital output. ra2/an2/v ref -ra2 0 o dig lata<2> data output; not affected by analog input. disabled when cv ref output enabled. 1 i ttl porta<2> data input. disabled when analog functions enabled; disabled when cv ref output enabled. an2 1 i ana a/d input channel 2. default input configuration on por; not affected by analog output. v ref - 1 i ana comparator voltage reference low input and a/d voltage reference low input. ra3/an3/v ref +ra3 0 o dig lata<3> data output; not affected by analog input. 1 i ttl porta<3> data input; disabled when analog input enabled. an3 1 i ana a/d input channel 3. default input configuration on por. v ref + 1 i ana comparator voltage reference hi gh input and a/d voltage reference high input. ra4/t0cki ra4 0 o dig lata<4> data output 1 i st porta<4> data input; default configuration on por. t0cki x i st timer0 clock input. ra5/an4/hlvdin ra5 0 o dig lata<5> data output; not affected by analog input. 1 i ttl porta<5> data input; disabled when analog input enabled. an4 1 i ana a/d input channel 4. default configuration on por. hlvdin 1 i ana high/low-voltage detect external trip point input. osc2/clko/ra6 osc2 x o ana main oscillator feedback output connection (xt, hs and lp modes). clko x o dig system cycle clock output (f osc /4) in all oscillator modes except rcio, intio2 and ecio. ra6 0 o dig lata<6> data output. enabled in rcio, intio2 and ecio modes only. 1 i ttl porta<6> data input. enabled in rcio, intio2 and ecio modes only. osc1/clki/ra7 osc1 x i ana main oscillator input connection. clki x i ana main clock input connection. ra7 0 o dig lata<7> data output. disabled in external oscillator modes. 1 i ttl porta<7> data input. disabled in external oscillator modes. legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st= schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option).
? 2004 microchip technology inc. preliminary ds39635a-page 119 pic18f6310/6410/8310/8410 table 10-2: summary of registers associated with porta name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page porta ra7 (1) ra6 (1) ra5 ra4 ra3 ra2 ra1 ra0 60 lata lata7 (1) lata6 (1) lata data output register 60 trisa trisa7 (1) trisa6 (1) porta data direction register 60 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 58 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by porta. note 1: ra7:ra6 and their associated latch and data direction bits are enabled as i/o pins based on oscillator configuration; otherwise, they are read as ? 0 ?.
pic18f6310/6410/8310/8410 ds39635a-page 120 preliminary ? 2004 microchip technology inc. 10.2 portb, trisb and latb registers portb is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latb) is also memory mapped. read-modify-write operations on the latb register read and write the latched output value for portb. example 10-2: initializing portb each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is performed by clearing bit rbpu (intcon2<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. four of the portb pins (rb7:rb4) have an interrupt-on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt-on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are ored together to generate the rb port change interrupt with flag bit, rbif (intcon<0>). this interrupt can wake the device from power managed modes. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb (except with the movff (any), portb instruction). this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. for 80-pin devices, rb3 can be configured as the alternate peripheral pin for the ccp2 module by clearing the ccp2mx configuration bit. this applies only when the device is in one of the operating modes other than the default microcontroller mode. if the device is in microcontroller mode, the alternate assignment for ccp2 is re7. as with other ccp2 con- figurations, the user must ensure that the trisb<3> bit is set appropriately for the intended operation. clrf portb ; initialize portb by ; clearing output ; data latches clrf latb ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs
? 2004 microchip technology inc. preliminary ds39635a-page 121 pic18f6310/6410/8310/8410 table 10-3: portb functions pin name function tris setting i/o i/o type description rb0/int0 rb0 0 o dig latb<0> data output. 1 i ttl portb<0> data input; weak pull-up when rbpu bit is cleared. int0 1 i st external interrupt 0 input. rb1/int1 rb1 0 o dig latb<1> data output. 1 i ttl portb<1> data input; weak pull-up when rbpu bit is cleared. int1 1 i st external interrupt 1 input. rb2/int2 rb2 0 o dig latb<2> data output. 1 i ttl portb<2> data input; weak pull-up when rbpu bit is cleared. int2 1 i st external interrupt 2 input. rb3/int3/ ccp2 rb3 0 o dig latb<3> data output. 1 i ttl portb<3> data input; weak pull-up when rbpu bit is cleared. int3 1 i st external interrupt 3 input. ccp2 (1) 0 o dig ccp2 compare output and ccp2 pwm output; takes priority over port data. 1 i st ccp2 capture input. rb4/kbi0 rb4 0 o dig latb<4> data output. 1 i ttl portb<4> data input; weak pull-up when rbpu bit is cleared. kbi0 1 i ttl interrupt on pin change. rb5/kbi1 rb5 0 o dig latb<5> data output 1 i ttl portb<5> data input; weak pull-up when rbpu bit is cleared. kbi1 1 i ttl interrupt on pin change. rb6/kbi2/pgc rb6 0 o dig latb<6> data output 1 i ttl portb<6> data input; weak pull-up when rbpu bit is cleared. kbi2 1 i ttl interrupt on pin change. pgc x i st serial execution (icsp?) clock input for icsp and icd operation (2) . rb7/kbi3/pgd rb7 0 o dig latb<7> data output. 1 i ttl portb<7> data input; weak pull-up when rbpu bit is cleared. kbi3 1 i ttl interrupt on pin change. pgd x o dig serial execution data output for icsp and icd operation (2) . x i st serial execution data input for icsp and icd operation (2) . legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: alternate assignment for ccp2 when the ccp2mx conf iguration bit is cleared (microprocessor, extended microcontroller and microcontroller with boot block m odes, 80-pin devices only). default assignment is rc1. 2: all other pin functions are disabled when icsp or icd operations are enabled.
pic18f6310/6410/8310/8410 ds39635a-page 122 preliminary ? 2004 microchip technology inc. table 10-4: summary of registers associated with portb name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 60 latb latb data output register 60 trisb portb data direction register 60 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 57 intcon3 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if 57 legend: shaded cells are not used by portb.
? 2004 microchip technology inc. preliminary ds39635a-page 123 pic18f6310/6410/8310/8410 10.3 portc, trisc and latc registers portc is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisc. setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latc) is also memory mapped. read-modify-write operations on the latc register read and write the latched output value for portc. portc is multiplexed with several peripheral functions (table 10-5). the pins have schmitt trigger input buffers. rc1 is normally configured by configuration bit ccp2mx as the default peripheral pin of the ccp2 module (default/erased state, ccp2mx = 1 ). when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the contents of the trisc register are affected by peripheral overrides. reading trisc always returns the current contents, even though a peripheral device may be overriding one or more of the pins. example 10-3: initializing portc note: on a power-on reset, these pins are configured as digital inputs. clrf portc ; initialize portc by ; clearing output ; data latches clrf latc ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs
pic18f6310/6410/8310/8410 ds39635a-page 124 preliminary ? 2004 microchip technology inc. table 10-5: portc functions pin name function tris setting i/o i/o type description rc0/t1oso/t13cki rc0 0 o dig latc<0> data output. 1 i st portc<0> data input. t1oso x o ana timer1 oscillator output; enabled when timer1 oscillator enabled. disables digital i/o. t13cki 1 i st timer1/timer3 counter input. rc1/t1osi/ccp2 rc1 0 o dig latc<1> data output. 1 i st portc<1> data input. t1osi x i ana timer1 oscillator input; enabled when timer1 oscillator enabled. disables digital i/o. ccp2 (1) 0 o dig ccp2 compare output and ccp2 pwm output; takes priority over port data. 1 i st ccp2 capture input rc2/ccp1 rc2 0 o dig latc<2> data output. 1 i st portc<2> data input. ccp1 0 o dig ccp1 compare output and ccp1 pwm output; takes priority over port data. 1 i st ccp1 capture input. rc3/sck/scl rc3 0 o dig latc<3> data output. 1 i st portc<3> data input. sck 0 o dig spi? clock output (mssp module); takes priority over port data. 1 i st spi clock input (mssp module). scl 0 odigi 2 c? clock output (mssp module); takes priority over port data. 1 isti 2 c clock input (mssp module); input type depends on module setting. rc4/sdi/sda rc4 0 o dig latc<4> data output. 1 i st portc<4> data input. sdi 1 i st spi data input (mssp module). sda 1 odigi 2 c data output (mssp module); takes priority over port data. 1 isti 2 c data input (mssp module); input type depends on module setting. rc5/sdo rc5 0 o dig latc<5> data output. 1 i st portc<5> data input. sdo 0 o dig spi data output (mssp module); takes priority over port data. rc6/tx1/ck1 rc6 0 o dig latc<6> data output. 1 i st portc<6> data input. tx1 1 o dig synchronous serial data output (eu sart module); takes priority over port data. ck1 1 o dig synchronous serial data input (eusart module). user must configure as an input. 1 i st synchronous serial clock input (eusart module). rc7/rx1/dt1 rc7 0 o dig latc<7> data output. 1 i st portc<7> data input. rx1 1 i st asynchronous serial receive data input (eusart module) dt1 1 o dig synchronous serial data output (eu sart module); takes priority over port data. 1 i st synchronous serial data input (eusart module). user must configure as an input. legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: default assignment for ccp2 when ccp 2mx configuration bit is set.
? 2004 microchip technology inc. preliminary ds39635a-page 125 pic18f6310/6410/8310/8410 table 10-6: summary of registers associated with portc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 60 latc latc data output register 60 trisc portc data direction register 60 legend: shaded cells are not used by portc.
pic18f6310/6410/8310/8410 ds39635a-page 126 preliminary ? 2004 microchip technology inc. 10.4 portd, trisd and latd registers portd is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisd. setting a trisd bit (= 1 ) will make the corresponding portd pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisd bit (= 0 ) will make the corresponding portd pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latd) is also memory mapped. read-modify-write operations on the latd register read and write the latched output value for portd. all pins on portd are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. in 80-pin devices, portd is multiplexed with the system bus as part of the external memory interface. i/o port and other functions are only available when the interface is disabled by setting the ebdis bit (memcon<7>). when the interface is enabled, portd is the low-order byte of the multiplexed address/data bus (ad7:ad0). the trisd bits are also overridden. portd can also be configured to function as an 8-bit wide parallel microprocessor port by setting the pspmode control bit (pspcon<4>). in this mode, parallel port data takes priority over other digital i/o (but not the external memory interface). when the parallel port is active, the input buffers are ttl. for more information, refer to section 10.10 ?parallel slave port? . example 10-4: initializing portd note: on a power-on reset, these pins are configured as digital inputs. clrf portd ; initialize portd by ; clearing output ; data latches clrf latd ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisd ; set rd<3:0> as inputs ; rd<5:4> as outputs ; rd<7:6> as inputs
? 2004 microchip technology inc. preliminary ds39635a-page 127 pic18f6310/6410/8310/8410 table 10-7: portd functions pin name function tris setting i/o i/o type description rd0/ad0/psp0 rd0 0 o dig latd<0> data output. 1 i st portd<0> data input. ad0 (2) x o dig external memory interface, address/data bit 0 output (1) . x i ttl external memory interface, data bit 0 input (1) . psp0 x o dig psp read data output (latd<0>); takes priority over port data. x i ttl psp write data input. rd1/ad1/psp1 rd1 0 o dig latd<1> data output. 1 i st portd<1> data input. ad1 (2) x o dig external memory interface, address/data bit 1 output (1) . x i ttl external memory interface, data bit 1 input (1) . psp1 x o dig psp read data output (latd<1>); takes priority over port data. x i ttl psp write data input. rd2/ad2/psp2 rd2 0 o dig latd<2> data output. 1 i st portd<2> data input. ad2 (2) x o dig external memory interface, address/data bit 2 output (1) . x i ttl external memory interface, data bit 2 input (1) . psp2 x o dig psp read data output (latd<2>); takes priority over port data. x i ttl psp write data input. rd3/ad3/psp3 rd3 0 o dig latd<3> data output. 1 i st portd<3> data input. ad3 (2) x o dig external memory interface, address/data bit 3 output (1) . x i ttl external memory interface, data bit 3 input (1) . psp3 x o dig psp read data output (latd<3>); takes priority over port data. x i ttl psp write data input. rd4/ad4/psp4 rd4 0 o dig latd<4> data output. 1 i st portd<4> data input. ad4 (2) x o dig external memory interface, address/data bit 4 output (1) . x i ttl external memory interface, data bit 4 input (1) . psp4 x o dig psp read data output (latd<4>); takes priority over port data. x i ttl psp write data input. rd5/ad5/psp5 rd5 0 o dig latd<5> data output. 1 i st portd<5> data input. ad5 (2) x o dig external memory interface, address/data bit 5 output (1) . x i ttl external memory interface, data bit 5 input (1) . psp5 x o dig psp read data output (latd<5>); takes priority over port data. x i ttl psp write data input. rd6/ad6/psp6 rd6 0 o dig latd<6> data output. 1 i st portd<6> data input. ad6 (2) x o dig-3 external memory interface, address/data bit 6 output (1) . x i ttl external memory interface, data bit 6 input (1) . psp6 x o dig psp read data output (latd<6>); takes priority over port data. x i ttl psp write data input. legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: external memory interface i/o takes priority over all other digital and psp i/o. 2: implemented on 80-pin devices only.
pic18f6310/6410/8310/8410 ds39635a-page 128 preliminary ? 2004 microchip technology inc. table 10-8: summary of registers associated with portd rd7/ad7/psp7 rd7 0 o dig latd<7> data output. 1 i st portd<7> data input. ad7 (2) x o dig external memory interface, address/data bit 7 output (1) . x i ttl external memory interface, data bit 7 input (1) . psp7 x o dig psp read data output (latd<7>); takes priority over port data. x i ttl psp write data input. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 60 latd latd data output register 60 trisd portd data direction register 60 table 10-7: portd functions (continued) pin name function tris setting i/o i/o type description legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: external memory interface i/o takes priority over all other digital and psp i/o. 2: implemented on 80-pin devices only.
? 2004 microchip technology inc. preliminary ds39635a-page 129 pic18f6310/6410/8310/8410 10.5 porte, trise and late registers porte is an 8-bit wide, bidirectional port. the corresponding data direction register is trise. setting a trise bit (= 1 ) will make the corresponding porte pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trise bit (= 0 ) will make the corresponding porte pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (late) is also memory mapped. read-modify-write operations on the late register read and write the latched output value for porte. all pins on porte are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. when the device is operating in microcontroller mode, pin re7 can be configured as the alternate peripheral pin for the ccp2 module. this is done by clearing the ccp2mx configuration bit. in 80-pin devices, porte is multiplexed with the system bus as part of the external memory interface. i/o port and other functions are only available when the interface is disabled by setting the ebdis bit (memcon<7>). when the interface is enabled (80-pin devices only), porte is the high-order byte of the multiplexed address/data bus (ad15:ad8). the trise bits are also overridden. when the parallel slave port is active on portd, three of the porte pins (re0/ad8/rd , re1/ad9/wr and re2/ad10/cs ) are configured as digital control inputs for the port. the control functions are summarized in table 10-9. the reconfiguration occurs automatically when the pspmode control bit (pspcon<4>) is set. users must still make certain the the corresponding trise bits are set to configure these pins as digital inputs. example 10-5: initializing porte note: on a power-on reset, these pins are configured as digital inputs. clrf porte ; initialize porte by ; clearing output ; data latches clrf late ; alternate method ; to clear output ; data latches movlw 03h ; value used to ; initialize data ; direction movwf trise ; set re<1:0> as inputs ; re<7:2> as outputs
pic18f6310/6410/8310/8410 ds39635a-page 130 preliminary ? 2004 microchip technology inc. table 10-9: porte functions pin name function tris setting i/o i/o type description re0/ad8/rd re0 0 o dig late<0> data output. 1 i st porte<0> data input. ad8 (3) x o dig external memory interface, address/data bit 8 output (2) . x i ttl external memory interface, data bit 8 input (2) . rd 1 i ttl parallel slave port read enable control input. re1/ad9/wr re1 0 o dig late<1> data output. 1 i st porte<1> data input. ad9 (3) x o dig external memory interface, address/data bit 9 output (2) . x i ttl external memory interface, data bit 9 input (2) . wr 1 i ttl parallel slave port write enable control input. re2/ad10/cs re2 0 o dig late<2> data output. 1 i st porte<2> data input. ad10 (3) x o dig external memory interface, address/data bit 10 output (2) . x i ttl external memory interface, data bit 10 input (2) . cs 1 i ttl parallel slave port chip select control input. re3/ad11 re3 0 o dig late<3> data output. 1 i st porte<3> data input. ad11 (3) x o dig external memory interface, address/data bit 11 output (2) . x i ttl external memory interface, data bit 11 input (2) . re4/ad12 re4 0 o dig late<4> data output. 1 i st porte<4> data input. ad12 (3) x o dig external memory interface, address/data bit 12 output (2) . x i ttl external memory interface, data bit 12 input (2) . re5/ad13 re5 0 o dig late<5> data output. 1 i st porte<5> data input. ad13 (3) x o dig external memory interface, address/data bit 13 output (2) . x i ttl external memory interface, data bit 13 input (2) . re6/ad14 re6 0 o dig late<6> data output. 1 i st porte<6> data input. ad14 (3) x o dig external memory interface, address/data bit 14 output (2) . x i ttl external memory interface, data bit 14 input (2) . re7/ccp2/ad15 re7 0 o dig late<7> data output. 1 i st porte<7> data input. ccp2 (1) 0 o dig ccp2 compare output and ccp2 pwm output; takes priority over port data. 1 i st ccp2 capture input. ad15 (3) x o dig external memory interface, address/data bit 15 output (2) . x i ttl external memory interface, data bit 15 input (2) . legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: alternate assignment for ccp2 when ccp2mx configuration bit is cleared (all devices in microcontroller mode). 2: external memory interface i/o takes priority over all other digital and psp i/o. 3: implemented on 80-pin devices only.
? 2004 microchip technology inc. preliminary ds39635a-page 131 pic18f6310/6410/8310/8410 table 10-10: summary of registers associated with porte name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page porte re7 re6 re5 re4 re3 re2 re1 re0 60 late late data output register 60 trise porte data direction bits 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by porte.
pic18f6310/6410/8310/8410 ds39635a-page 132 preliminary ? 2004 microchip technology inc. 10.6 portf, latf and trisf registers portf is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisf. setting a trisf bit (= 1 ) will make the corresponding portf pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisf bit (= 0 ) will make the corresponding portf pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latf) is also memory mapped. read-modify-write operations on the latf register read and write the latched output value for portf. all pins on portf are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. portf is multiplexed with several analog peripheral functions, including the a/d converter and comparator inputs, as well as the comparator outputs. pins rf2 through rf6 may be used as comparator inputs or outputs by setting the appropriate bits in the cmcon register. to use rf3:rf6 as digital inputs, it is also necessary to turn off the comparators. example 10-6: initializing portf note: on a power-on reset, ra5 and ra3:ra0 are configured as analog inputs and read as ? 0 ?. ra4 is configured as a digital input. note 1: on a power-on reset, the rf6:rf0 pins are configured as inputs and read as ? 0 ?. 2: to configure portf as digital i/o, turn off comparators and set adcon1 value. clrf portf ; initialize portf by ; clearing output ; data latches clrf latf ; alternate method ; to clear output ; data latches movlw 0x07 ; movwf cmcon ; turn off comparators movlw 0x0f ; movwf adcon1 ; set portf as digital i/o movlw 0xcf ; value used to ; initialize data ; direction movwf trisf ; set rf3:rf0 as inputs ; rf5:rf4 as outputs ; rf7:rf6 as inputs
? 2004 microchip technology inc. preliminary ds39635a-page 133 pic18f6310/6410/8310/8410 table 10-11: portf functions table 10-12: summary of registers associated with portf pin name function tris setting i/o i/o type description rf0/an5 rf0 0 o dig latf<0> data output; not affected by analog input. 1 i st portf<0> data input; disabled when analog input enabled. an5 1 i ana a/d input channel 5. default configuration on por. rf1/an6/c2out rf1 0 o dig latf<1> data output; not affected by analog input. 1 i st portf<1> data input; disabled when analog input enabled. an6 1 i ana a/d input channel 6. default configuration on por. c2out 0 o dig comparator 2 output; takes priority over port data. rf2/an7/c1out rf2 0 o dig latf<2> data output; not affected by analog input. 1 i st portf<2> data input; disabled when analog input enabled. an7 1 i ana a/d input channel 7. default configuration on por. c1out 0 o ttl comparator 1 output; takes priority over port data. rf3/an8 rf3 0 o dig latf<3> data output; not affected by analog input. 1 i st portf<3> data input; disabled when analog input enabled. an8 1 i ana a/d input channel 8 and comparator c2+ input. default input configuration on por; not affected by analog output. rf4/an9 rf4 0 o dig latf<4> data output; not affected by analog input. 1 i st portf<4> data input; disabled when analog input enabled. an9 1 i ana a/d input channel 9 and comparator c2- input. default input configuration on por; does not affect digital output. rf5/an10/cv ref rf5 0 o dig latf<5> data output; not affected by analog input. disabled when cv ref output enabled. 1 i st portf<5> data input; disabled when analog input enabled. disabled when cv ref output enabled an10 1 i ana a/d input channel 10 and comparator c1+ input. default input configuration on por. cv ref x o ana comparator voltage reference output. enabling this feature disables digital i/o. rf6/an11 rf6 0 o dig latf<6> data output; not affected by analog input. 1 i st portf<6> data input; disabled when analog input enabled. an11 1 i ana a/d input channel 11 and comparator c1- input. default input configuration on por; does not affect digital output. rf7/ss rf7 0 o dig latf<7> data output. 1 i st portf<7> data input. ss 1 i ttl slave select input for ssp (mssp module). legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page trisf portf data direction control register 60 portf read portf pin/write portf data latch 60 latf read portf data latch/write portf data latch 60 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 58 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 59 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by portf.
pic18f6310/6410/8310/8410 ds39635a-page 134 preliminary ? 2004 microchip technology inc. 10.7 portg, trisg and latg registers portg is a 6-bit wide, bidirectional port. the corre- sponding data direction register is trisg. setting a trisg bit (= 1 ) will make the corresponding portg pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisg bit (= 0 ) will make the corresponding portg pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latg) is also memory mapped. read-modify-write operations on the latg register, read and write the latched output value for portg. portg is multiplexed with usart functions (table 10-13). portg pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portg pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the pin override value is not loaded into the tris register. this allows read-modify-write of the tris register without concern due to peripheral overrides. the sixth pin of portg (rg5/mclr /v pp ) is an input only pin. its operation is controlled by the mclre configuration bit. when selected as a port pin (mclre = 0 ), it functions as a digital input only pin; as such, it does not have tris or lat bits associated with its operation. otherwise, it functions as the device?s master clear input. in either configuration, rg5 also functions as the programming voltage input during programming. example 10-7: initializing portg note: on a power-on reset, rg5 is enabled as a digital input only if master clear functionality is disabled. all other 5 pins are configured as digital inputs. clrf portg ; initialize portg by ; clearing output ; data latches clrf latg ; alternate method ; to clear output ; data latches movlw 0x04 ; value used to ; initialize data ; direction movwf trisg ; set rg1:rg0 as outputs ; rg2 as input ; rg4:rg3 as inputs
? 2004 microchip technology inc. preliminary ds39635a-page 135 pic18f6310/6410/8310/8410 table 10-13: portg functions table 10-14: summary of registers associated with portg pin name function tris setting i/o i/o type description rg0/ccp3 rg0 0 o dig latg<0> data output. 1 i st portg<0> data input. ccp3 0 o dig ccp3 compare and pwm output; takes priority over port data. 1 i st ccp3 capture input. rg1/tx2/ck2 r21 0 o dig latg<1> data output. 1 i st portg<1> data input. tx2 1 o dig synchronous serial data output (aus art module); takes priority over port data. ck2 1 o dig synchronous serial data input (ausart module). user must configure as an input. 1 i st synchronous serial clock input (ausart module). rg2/rx2/dt2 rg2 0 o dig latg<2> data output. 1 i st portg<2> data input. rx2 1 i st asynchronous serial receive data input (ausart module). dt2 1 o dig synchronous serial data output (aus art module); takes priority over port data. 1 i st synchronous serial data input (ausart module). user must configure as an input. rg3 rg3 0 o dig latg<3> data output. 1 i st portg<3> data input. rg4 rg4 0 o dig latg<4> data output. 1 i st portg<4> data input. rg5/mclr /v pp rg5 ? (1) i st portg<5> data input; enabled when mclre configuration bit is clear. mclr ? i st external master clear input; enabl ed when mclre configuration bit is set. v pp ? i ana high-voltage detection; used for icsp? mode entry detection. always available, regardless of pin mode. legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: rg5 does not have a corresponding trisg bit. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portg ? ?rg5 (1) read portg pin/write portg data latch 60 latg ? ? ? latg data output register 60 trisg ? ? ? data direction control register for portg 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by portg. note 1: rg5 is available as an input only when mclr is disabled.
pic18f6310/6410/8310/8410 ds39635a-page 136 preliminary ? 2004 microchip technology inc. 10.8 porth, lath and trish registers porth is an 8-bit wide, bidirectional i/o port. the cor- responding data direction register is trish. setting a trish bit (= 1 ) will make the corresponding porth pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trish bit (= 0 ) will make the corresponding porth pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (lath) is also memory mapped. read-modify-write operations on the lath register, read and write the latched output value for porth. all pins on porth are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. when the external memory interface is enabled, four of the porth pins function as the high-order address lines for the interface. the address output from the interface takes priority over other digital i/o. the corresponding trish bits are also overridden. example 10-8: initializing porth note: porth is available only on pic18f8310/8410 devices. note: on a power-on reset, these pins are configured as digital inputs. clrf porth ; initialize porth by ; clearing output ; data latches clrf lath ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trish ; set rh3:rh0 as inputs ; rh5:rh4 as outputs ; rh7:rh6 as inputs
? 2004 microchip technology inc. preliminary ds39635a-page 137 pic18f6310/6410/8310/8410 table 10-15: porth functions table 10-16: summary of registers associated with porth pin name function tris setting i/o i/o type description rh0/ad16 rh0 0 o dig lath<0> data output. 1 i st porth<0> data input. ad16 x o dig external memory interface, addre ss line 16. takes priority over port data. rh1/ad17 rh1 0 o dig lath<1> data output. 1 i st porth<1> data input. ad17 x o dig external memory interface, addre ss line 17. takes priority over port data. rh2/ad18 rh2 0 o dig lath<2> data output. 1 i st porth<2> data input. ad18 x o dig external memory interface, addre ss line 18. takes priority over port data. rh3/ad19 rh3 0 o dig lath<3> data output. 1 i st porth<3> data input. ad19 x o dig external memory interface, addre ss line 19. takes priority over port data. rh4 rh4 0 o dig lath<4> data output. 1 i st porth<4> data input. rh5 rh5 0 o dig lath<5> data output. 1 i st porth<5> data input. rh6 rh6 0 o dig lath<6> data output. 1 i st porth<6> data input. rh7 rh7 0 o dig lath<7> data output. 1 i st porth<7> data input. legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page trish porth data direction control register 59 porth read porth pin/write porth data latch 60 lath read porth data latch/write porth data latch 60
pic18f6310/6410/8310/8410 ds39635a-page 138 preliminary ? 2004 microchip technology inc. 10.9 portj, trisj and latj registers portj is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisj. setting a trisj bit (= 1 ) will make the corresponding portj pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisj bit (= 0 ) will make the corresponding portj pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latj) is also memory mapped. read-modify-write operations on the latj register, read and write the latched output value for portj. all pins on portj are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. when the external memory interface is enabled, all of the portj pins function as control outputs for the interface. this occurs automatically when the interface is enabled by clearing the ebdis control bit (memcon<7>). the trisj bits are also overridden. example 10-9: initializing portj note: portj is available only on pic18f8310/8410 devices. note: on a power-on reset, these pins are configured as digital inputs. clrf portj ; initialize portg by ; clearing output ; data latches clrf latj ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisj ; set rj3:rj0 as inputs ; rj5:rj4 as output ; rj7:rj6 as inputs
? 2004 microchip technology inc. preliminary ds39635a-page 139 pic18f6310/6410/8310/8410 table 10-17: portj functions table 10-18: summary of registers associated with portj pin name function tris setting i/o i/o type description rj0/ale rj0 0 o dig latj<0> data output. 1 i st portj<0> data input. ale x o dig external memory interface address latch enable control output; takes priority over digital i/o. rj1/oe rj1 0 o dig latj<1> data output. 1 i st portj<1> data input. oe x o dig external memory interface output enable control output; takes priority over digital i/o. rj2/wrl rj2 0 o dig latj<2> data output. 1 i st portj<2> data input. wrl x o dig external memory bus write low byte control; takes priority over digital i/o. rj3/wrh rj3 0 o dig latj<3> data output. 1 i st portj<3> data input. wrh x o dig external memory interface write high byte control output; takes priority over digital i/o. rj4/ba0 rj4 0 o dig latj<4> data output. 1 i st portj<4> data input. ba0 x o dig external memory interface byte address 0 control output; takes priority over digital i/o. rj5/ce rj5 0 o dig latj<5> data output. 1 i st portj<5> data input. ce x o dig external memory interface chip enable control output; takes priority over digital i/o. rj6/lb rj6 0 o dig latj<6> data output. 1 i st portj<6> data input. lb x o dig external memory interface lower byte enable control output; takes priority over digital i/o. rj7/ub rj7 0 o dig latj<7> data output. 1 i st portj<7> data input. ub x o dig external memory interface upper byte enable control output; takes priority over digital i/o. legend: pwr = power supply, o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portj read portj pin/write portj data latch 60 latj latj data output register 60 trisj data direction control register for portj 59
pic18f6310/6410/8310/8410 ds39635a-page 140 preliminary ? 2004 microchip technology inc. 10.10 parallel slave port portd can also function as an 8-bit wide parallel slave port, or microprocessor port, when control bit pspmode (pspcon<4>) is set. it is asynchronously readable and writable by the external world through rd control input pin, re0/rd and wr control input pin, re1/wr . the psp can directly interface to an 8-bit micro- processor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit pspmode enables port pin re0/rd to be the rd input, re1/wr to be the wr input and re2/cs to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (set). a write to the psp occurs when both the cs and wr lines are first detected low and ends when either are detected high. the pspif and ibf flag bits are both set when the write ends. a read from the psp occurs when both the cs and rd lines are first detected low. the data in portd is read out and the obf bit is set. if the user writes new data to portd to set obf, the data is immediately read out; however, the obf bit is not set. when either the cs or rd lines are detected high, the portd pins return to the input state and the pspif bit is set. user applications should wait for pspif to be set before servicing the psp; when this happens, the ibf and obf bits can be polled and the appropriate action taken. the timing for the control signals in write and read modes is shown in figure 10-3 and figure 10-4, respectively. figure 10-2: portd and porte block diagram (parallel slave port) note: for pic18f8310/8410 devices, the parallel slave port is available only in microcontroller mode. data bus wr latd rdx q d ck en qd en rd portd pin one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr note: i/o pin has protection diodes to v dd and v ss . ttl ttl ttl ttl or portd rd latd data latch tris latch
? 2004 microchip technology inc. preliminary ds39635a-page 141 pic18f6310/6410/8310/8410 register 10-1: pspcon: parallel slave port control register figure 10-3: parallel slave port write waveforms r-0 r-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ibf obf ibov pspmode ? ? ? ? bit 7 bit 0 bit 7 ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6 obf: output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov: input buffer overflow detect bit 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode: parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0>
pic18f6310/6410/8310/8410 ds39635a-page 142 preliminary ? 2004 microchip technology inc. figure 10-4: parallel slave port read waveforms table 10-19: registers associated with parallel slave port q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0> name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portd portd data latch when written; port pins when read 60 latd latd data output bits 60 trisd portd data direction bits 60 porte porte data latch when written; port pins when read 60 late late data output bits 60 trise porte data direction bits 60 pspcon ibf obf ibov pspmode ? ? ? ?59 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the parallel slave port.
? 2004 microchip technology inc. preliminary ds39635a-page 143 pic18f6310/6410/8310/8410 11.0 timer0 module the timer0 module incorporates the following features: software selectable operation as a timer or counter in both 8-bit or 16-bit modes readable and writable registers dedicated 8-bit software programmable prescaler selectable clock source (internal or external) edge select for external clock interrupt-on-overflow the t0con register (register 11-1) controls all aspects of the module?s operation, including the prescale selection. it is both readable and writable. a simplified block diagram of the timer0 module in 8-bit mode is shown in figure 11-1. figure 11-2 shows a simplified block diagram of the timer0 module in 16-bit mode. register 11-1: t0con: timer0 control register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 bit 7 bit 0 bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit : timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2-0 t0ps2:t0ps0 : timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 144 preliminary ? 2004 microchip technology inc. 11.1 timer0 operation timer0 can operate as either a timer or a counter; the mode is selected by clearing the t0cs bit (t0con<5>). in timer mode (t0cs = 0 ), the module increments on every clock by default, unless a different prescaler value is selected (see section 11.3 ?prescaler? ). if the tmr0 register is written to, the increment is inhibited for the fol- lowing two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. the counter mode is selected by setting the t0cs bit (= 1 ). in counter mode, timer0 increments either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the timer0 source edge select bit, t0se (t0con<4>); clearing this bit selects the rising edge. restrictions on the external clock input are discussed below. an external clock source can be used to drive timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the internal phase clock (t osc ). there is a delay between synchronization and the onset of incrementing the timer/counter. 11.2 timer0 reads and writes in 16-bit mode tmr0h is not the actual high byte of timer0 in 16-bit mode; it is actually a buffered version of the real high byte of timer0, which is not directly readable nor writable (refer to figure 11-2). tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this provides the ability to read all 16 bits of timer0, without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. similarly, a write to the high byte of timer0 must also take place through the tmr0h buffer register. the high byte is updated with the contents of tmr0h when a write occurs to tmr0l. this allows all 16 bits of timer0 to be updated at once. figure 11-1: timer0 block diagram (8-bit mode) figure 11-2: timer0 block diagram (16-bit mode) note: upon reset, timer0 is enabled in 8-bit mode wit h clock input from t0cki maximum prescale. t0cki pin t0se 0 1 0 1 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) internal data bus psa t0ps2:t0ps0 set tmr0if on overflow 3 8 8 note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki maximum prescale. t0cki pin t0se 0 1 0 1 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) internal data bus 8 psa t0ps2:t0ps0 set tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l 8
? 2004 microchip technology inc. preliminary ds39635a-page 145 pic18f6310/6410/8310/8410 11.3 prescaler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not directly readable or writable; its value is set by the psa and t0ps2:t0ps0 bits (t0con<3:0>), which determine the prescaler assignment and prescale ratio. clearing the psa bit assigns the prescaler to the timer0 module. when it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0, movwf tmr0, bsf tmr0, etc.) clear the prescaler count. 11.3.1 switching prescaler assignment the prescaler assignment is fully under software control and can be changed ?on-the-fly? during program execution. 11.4 timer0 interrupt the tmr0 interrupt is generated when the tmr0 register overflows from ffh to 00h in 8-bit mode, or from ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if flag bit. the interrupt can be masked by clearing the tmr0ie bit (intcon<5>). before re- enabling the interrupt, the tmr0if bit must be cleared in software by the interrupt service routine. since timer0 is shut down in sleep mode, the tmr0 interrupt cannot awaken the processor from sleep. table 11-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count, but will not change the prescaler assignment. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page tmr0l timer0 module low byte register 58 tmr0h timer0 module high byte register 58 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 58 trisa porta data direction register 60 legend: shaded cells are not used by timer0.
pic18f6310/6410/8310/8410 ds39635a-page 146 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 147 pic18f6310/6410/8310/8410 12.0 timer1 module the timer1 timer/counter module incorporates these features: software selectable operation as a 16-bit timer or counter readable and writable 8-bit registers (tmr1h and tmr1l) selectable clock source (internal or external) with device clock or timer1 oscillator internal options interrupt-on-overflow reset on ccp special event trigger device clock status flag (t1run) a simplified block diagram of the timer1 module is shown in figure 12-1. a block diagram of the module?s operation in read/write mode is shown in figure 12-2. the module incorporates its own low-power oscillator to provide an additional clocking option. the timer1 oscillator can also be used as a low-power clock source for the microcontroller in power managed operation. timer1 can also be used to provide real-time clock (rtc) functionality to applications with only a minimal addition of external components and code overhead. timer1 is controlled through the t1con control register (register 12-1). it also contains the timer1 oscillator enable bit (t1oscen). timer1 can be enabled or disabled by setting or clearing control bit, tmr1on (t1con<0>). register 12-1: t1con: timer1 control register r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer1 in one 16-bit operation 0 = enables register read/write of timer1 in two 8-bit operations bit 6 t1run: timer1 system clock status bit 1 = device clock is derived from timer1 oscillator 0 = device clock is derived from another source bit 5-4 t1ckps1:t1ckps0: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable bit 1 = timer1 oscillator is enabled 0 = timer1 oscillator is shut off the oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 t1sync : timer1 external clock input synchronization select bit when tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock when tmr1cs = 0 . bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t13cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 148 preliminary ? 2004 microchip technology inc. 12.1 timer1 operation timer1 can operate in one of these modes: timer synchronous counter asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). when tmr1cs is cleared (= 0 ), timer1 increments on every internal instruction cycle (f osc /4). when the bit is set, timer1 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. when timer1 is enabled, the rc1/t1osi and rc0/ t1oso/t13cki pins become inputs. this means the values of trisc<1:0> are ignored and the pins are read as ? 0 ?. figure 12-1: timer1 block diagram figure 12-2: timer1 block diagram (16-bit read/write mode) t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen (1) f osc /4 internal clock on/off prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t1oso/t13cki t1osi 1 0 tmr1on tmr1l set tmr1if on overflow tmr1 high byte clear tmr1 (ccp special event trigger) timer1 oscillator note 1: when enable bit, t1oscen, is cleared, the inverter and f eedback resistor are turned off to eliminate power drain. on/off timer1 t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen (1) f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t1oso/t13cki t1osi note 1: when enable bit, t1oscen, is cleared, the inverter and fee dback resistor are turned off to eliminate power drain. 1 0 tmr1l internal data bus 8 set tmr1if on overflow tmr1 tmr1h high byte 8 8 8 read tmr1l write tmr1l 8 tmr1on clear tmr1 (ccp special event trigger) timer1 oscillator on/off timer1
? 2004 microchip technology inc. preliminary ds39635a-page 149 pic18f6310/6410/8310/8410 12.2 timer1 16-bit read/write mode timer1 can be configured for 16-bit reads and writes (see figure 12-2). when the rd16 control bit (t1con<7>) is set, the address for tmr1h is mapped to a buffer register for the high byte of timer1. a read from tmr1l will load the contents of the high byte of timer1 into the timer1 high byte buffer. this provides the user with the ability to accurately read all 16 bits of timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. a write to the high byte of timer1 must also take place through the tmr1h buffer register. the timer1 high byte is updated with the contents of tmr1h when a write occurs to tmr1l. this allows a user to write all 16 bits to both the high and low bytes of timer1 at once. the high byte of timer1 is not directly readable or writable in this mode. all reads and writes must take place through the timer1 high byte buffer register. writes to tmr1h do not clear the timer1 prescaler. the prescaler is only cleared on writes to tmr1l. 12.3 timer1 oscillator an on-chip crystal oscillator circuit is incorporated between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting the timer1 oscillator enable bit, t1oscen (t1con<3>). the oscillator is a low-power circuit rated for 32 khz crystals. it will continue to run during all power managed modes. the circuit for a typical lp oscillator is shown in figure 12-3. table 12-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper start-up of the timer1 oscillator. figure 12-3: external components for the timer1 lp oscillator table 12-1: capacitor selection for the timer oscillator 12.3.1 using timer1 as a clock source the timer1 oscillator is also available as a clock source in power managed modes. by setting the clock select bits, scs1:scs0 (osccon<1:0>), to ? 01 ?, the device switches to sec_run mode; both the cpu and peripherals are clocked from the timer1 oscillator. if the idlen bit (osccon<7>) is cleared and a sleep instruction is executed, the device enters sec_idle mode. additional details are available in section 3.0 ?power managed modes? . whenever the timer1 oscillator is providing the clock source, the timer1 system clock status flag, t1run (t1con<6>), is set. this can be used to determine the controller?s current clocking mode. it can also indicate the clock source being currently used by the fail-safe clock monitor. if the clock monitor is enabled and the timer1 oscillator fails while providing the clock, polling the t1run bit will indicate whether the clock is being provided by the timer1 oscillator or another source. 12.3.2 low-power timer1 option the timer1 oscillator can operate at two distinct levels of power consumption based on device configuration. when the lpt1osc configuration bit is set, the timer1 oscillator operates in a low-power mode. when lpt1osc is not set, timer1 operates at a higher power level. power consumption for a particular mode is rela- tively constant, regardless of the device?s operating mode. the default timer1 configuration is the higher power mode. as the low-power timer1 mode tends to be more sensitive to interference, high noise environments may cause some oscillator instability. the low-power option is therefore best suited for low noise applications where power conservation is an important design consideration. note: see the notes with table 12-1 for additional information about capacitor selection. c1 c2 xtal pic18fxxxx t1osi t1oso 32.768 khz 33 pf 33 pf osc type freq c1 c2 lp 32 khz 27 pf (1) 27 pf (1) note 1: microchip suggests these values as a starting point in validating the oscillator circuit. 2: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: capacitor values are for design guidance only.
pic18f6310/6410/8310/8410 ds39635a-page 150 preliminary ? 2004 microchip technology inc. 12.3.3 timer1 oscillator layout considerations the timer1 oscillator circuit draws very little power during operation. due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. the oscillator circuit, shown in figure 12-3, should be located as close as possible to the microcontroller. there should be no circuits passing within the oscillator circuit boundaries other than v ss or v dd . if a high-speed circuit must be located near the oscilla- tor (such as the ccp1 pin in output compare or pwm mode, or the primary oscillator using the osc2 pin), a grounded guard ring around the oscillator circuit, as shown in figure 12-4, may be helpful when used on a single sided pcb, or in addition to a ground plane. figure 12-4: oscillator circuit with grounded guard ring 12.4 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the timer1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, tmr1if (pir1<0>). this interrupt can be enabled or disabled by setting or clearing the timer1 interrupt enable bit, tmr1ie (pie1<0>). 12.5 resetting timer1 using the ccp special event trigger if ccp1 or ccp2 is configured in compare mode to generate a special event trigger (ccp1m3:ccp1m0 or ccp2m3:ccp2m0 = 1011 ), this signal will reset timer1. the trigger from ccp2 will also start an a/d conversion if the a/d module is enabled (see section 15.3.4 ?special event triggers? for more information.). the module must be configured as either a timer or a synchronous counter to take advantage of this feature. when used this way, the ccprh:ccprl register pair effectively becomes a period register for timer1. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger, the write operation will take precedence. 12.6 using timer1 as a real-time clock adding an external lp oscillator to timer1 (such as the one described in section 12.3 ?timer1 oscillator? , above), gives users the option to include rtc function- ality to their applications. this is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. when operating in sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate rtc device and battery backup. the application code routine, rtcisr , shown in example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an interrupt service routine. incrementing the tmr1 reg- ister pair to overflow triggers the interrupt and calls the routine, which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 khz clock would take 2 seconds. to force the overflow at the required one-second intervals, it is necessary to preload it; the simplest method is to set the most sig- nificant bit of tmr1h with a bsf instruction. note that the tmr1l register is never preloaded or altered; doing so may introduce cumulative error over many cycles. for this method to be accurate, timer1 must operate in asynchronous mode and the timer1 overflow interrupt must be enabled (pie1<0> = 1 ), as shown in the routine rtcinit . the timer1 oscillator must also be enabled and running at all times. v dd osc1 v ss osc2 rc0 rc1 rc2 note: not drawn to scale. note: the special event triggers from the ccp2 module will not set the tmr1if interrupt flag bit (pir1<0>).
? 2004 microchip technology inc. preliminary ds39635a-page 151 pic18f6310/6410/8310/8410 example 12-1: implementing a real-time clock using a timer1 interrupt service table 12-2: registers associated with timer1 as a timer/counter rtcinit movlw 80h ; preload tmr1 register pair movwf tmr1h ; for 1 second overflow clrf tmr1l movlw b?00001111? ; configure for external clock, movwf t1osc ; asynchronous operation, external oscillator clrf secs ; initialize timekeeping registers clrf mins ; movlw .12 movwf hours bsf pie1, tmr1ie ; enable timer1 interrupt return rtcisr bsf tmr1h, 7 ; preload for 1 sec overflow bcf pir1, tmr1if ; clear interrupt flag incf secs, f ; increment seconds movlw .59 ; 60 seconds elapsed? cpfsgt secs return ; no, done clrf secs ; clear seconds incf mins, f ; increment minutes movlw .59 ; 60 minutes elapsed? cpfsgt mins return ; no, done clrf mins ; clear minutes incf hours, f ; increment hours movlw .23 ; 24 hours elapsed? cpfsgt hours return ; no, done movlw .01 ; reset hours to 1 movwf hours return ; done name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 tmr1l holding register for the least significant byte of the 16-bit tmr1 register 58 tmr1h holding register for the most significant byte of the 16-bit tmr1 register 58 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 58 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module.
pic18f6310/6410/8310/8410 ds39635a-page 152 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 153 pic18f6310/6410/8310/8410 13.0 timer2 module the timer2 timer module incorporates the following features: 8-bit timer and period registers (tmr2 and pr2, respectively) readable and writable (both registers) software programmable prescaler (1:1, 1:4 and 1:16) software programmable postscaler (1:1 through 1:16) interrupt on tmr2-to-pr2 match optional use as the shift clock for the mssp module the module is controlled through the t2con register (register 13-1), which enables or disables the timer and configures the prescaler and postscaler. timer2 can be shut off by clearing control bit, tmr2on (t2con<2>), to minimize power consumption. a simplified block diagram of the module is shown in figure 13-1. 13.1 timer2 operation in normal operation, tmr2 is incremented from 00h on each clock (f osc /4). a 2-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by-16 prescale options; these are selected by the prescaler control bits, t2ckps1:t2ckps0 (t2con<1:0>). the value of tmr2 is compared to that of the period regis- ter, pr2, on each clock cycle. when the two values match, the comparator generates a match signal as the timer output. this signal also resets the value of tmr2 to 00h on the next cycle and drives the output counter/ postscaler (see section 13.2 ?timer2 interrupt? ). the tmr2 and pr2 registers are both directly readable and writable. the tmr2 register is cleared on any device reset, while the pr2 register initializes at ffh. both the prescaler and postscaler counters are cleared on the following events: a write to the tmr2 register a write to the t2con register any device reset (power-on reset, mclr reset, watchdog timer reset, or brown-out reset) tmr2 is not cleared when t2con is written. register 13-1: t2con: time r2 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-3 t2outps3:t2outps0: timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0: timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 154 preliminary ? 2004 microchip technology inc. 13.2 timer2 interrupt timer2 also can generate an optional device interrupt. the timer2 output signal (tmr2-to-pr2 match) pro- vides the input for the 4-bit output counter/postscaler. this counter generates the tmr2 match interrupt flag which is latched in tmr2if (pir1<1>). the interrupt is enabled by setting the tmr2 match interrupt enable bit, tmr2ie (pie1<1>). a range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, t2outps3:t2outps0 (t2con<6:3>). 13.3 tmr2 output the unscaled output of tmr2 is available primarily to the ccp modules, where it is used as a time base for operations in pwm mode. timer2 can be optionally used as the shift clock source for the mssp module operating in spi mode. addi- tional information is provided in section 16.0 ?master synchronous serial port (mssp) module? . figure 13-1: timer2 block diagram table 13-1: registers associated with timer2 as a timer/counter name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 tmr2 timer2 module register 58 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 58 pr2 timer2 period register 58 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer2 module. comparator tmr2 output tmr2 postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 4 t2outps3:t2outps0 t2ckps1:t2ckps0 set tmr2if internal data bus 8 reset tmr2/pr2 8 8 (to pwm or mssp) match
? 2004 microchip technology inc. preliminary ds39635a-page 155 pic18f6310/6410/8310/8410 14.0 timer3 module the timer3 timer/counter module incorporates these features: software selectable operation as a 16-bit timer or counter readable and writable 8-bit registers (tmr3h and tmr3l) selectable clock source (internal or external), with device clock or timer1 oscillator internal options interrupt-on-overflow module reset on ccp special event trigger a simplified block diagram of the timer3 module is shown in figure 14-1. a block diagram of the module?s operation in read/write mode is shown in figure 14-2. the timer3 module is controlled through the t3con register (register 14-1). it also selects the clock source options for the ccp modules (see section 15.1.1 ?ccp modules and timer resources? for more information). register 14-1: t3con: time r3 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer3 in one 16-bit operation 0 = enables register read/write of timer3 in two 8-bit operations bit 6, 3 t3ccp2:t3cccp1: timer3 and timer1 to ccpx enable bits 11 = timer3 is the clock source for compare/capture of all ccp modules 10 = timer3 is the clock source for compare/capture of ccp3, timer1 is the clock source for compare/capture of ccp1 and ccp2 01 = timer3 is the clock source for compare/capture of ccp2 and ccp3, timer1 is the clock source for compare/capture of ccp1 00 = timer1 is the clock source for compare/capture of all ccp modules bit 5-4 t3ckps1:t3ckps0 : timer3 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 2 t3sync : timer3 external clock input synchronization control bit (not usable if the device clock comes from timer1/timer3.) when tmr3cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr3cs = 0 : this bit is ignored. timer3 uses the internal clock when tmr3cs = 0 . bit 1 tmr3cs: timer3 clock source select bit 1 = external clock input from timer1 oscillator or t13cki (on the rising edge after the first falling edge) 0 = internal clock (f osc /4) bit 0 tmr3on: timer3 on bit 1 = enables timer3 0 = stops timer3 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 156 preliminary ? 2004 microchip technology inc. 14.1 timer3 operation timer3 can operate in one of three modes: timer synchronous counter asynchronous counter the operating mode is determined by the clock select bit, tmr3cs (t3con<1>). when tmr3cs is cleared (= 0 ), timer3 increments on every internal instruction cycle (f osc /4). when the bit is set, timer3 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. as with timer1, the rc1/t1osi and rc0/t1oso/ t13cki pins become inputs when the timer1 oscillator is enabled. this means the values of trisc<1:0> are ignored and the pins are read as ? 0 ?. figure 14-1: timer3 block diagram figure 14-2: timer3 block diagram (16-bit read/write mode) t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen (1) f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t1oso/t13cki t1osi 1 0 tmr3on tmr3l set tmr3if on overflow tmr3 high byte timer1 oscillator note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. on/off timer3 ccp1/ccp2 special event trigger tccpx clear tmr3 t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen (1) f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t1oso/t13cki t1osi note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. 1 0 tmr3l internal data bus 8 set tmr3if on overflow tmr3 tmr3h high byte 8 8 8 read tmr3l write tmr3l 8 tmr3on ccp1/ccp2 special event trigger timer1 oscillator on/off timer3 timer1 clock input tccpx clear tmr3
? 2004 microchip technology inc. preliminary ds39635a-page 157 pic18f6310/6410/8310/8410 14.2 timer3 16-bit read/write mode timer3 can be configured for 16-bit reads and writes (see figure 14-2). when the rd16 control bit (t3con<7>) is set, the address for tmr3h is mapped to a buffer register for the high byte of timer3. a read from tmr3l will load the contents of the high byte of timer3 into the timer3 high byte buffer register. this provides the user with the ability to accurately read all 16 bits of timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. a write to the high byte of timer3 must also take place through the tmr3h buffer register. the timer3 high byte is updated with the contents of tmr3h when a write occurs to tmr3l. this allows a user to write all 16 bits to both the high and low bytes of timer3 at once. the high byte of timer3 is not directly readable or writable in this mode. all reads and writes must take place through the timer3 high byte buffer register. writes to tmr3h do not clear the timer3 prescaler. the prescaler is only cleared on writes to tmr3l. 14.3 using the timer1 oscillator as the timer3 clock source the timer1 internal oscillator may be used as the clock source for timer3. the timer1 oscillator is enabled by setting the t1oscen (t1con<3>) bit. to use it as the timer3 clock source, the tmr3cs bit must also be set. as previously noted, this also configures timer3 to increment on every rising edge of the oscillator source. the timer1 oscillator is described in section 12.0 ?timer1 module? . 14.4 timer3 interrupt the tmr3 register pair (tmr3h:tmr3l) increments from 0000h to ffffh and overflows to 0000h. the timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, tmr3if (pir2<1>). this interrupt can be enabled or disabled by setting or clearing the timer3 interrupt enable bit, tmr3ie (pie2<1>). 14.5 resetting timer3 using the ccp special event trigger if either the ccp1 or ccp2 modules is configured to generate a special event trigger in compare mode (ccp1m3:ccp1m0 or ccp2m3:ccp2m0 = 1011 ), this signal will reset timer3. the trigger of ccp2 will also start an a/d conversion if the a/d module is enabled (see section 15.3.4 ?special event triggers? for more information). the module must be configured as either a timer or synchronous counter to take advantage of this feature. when used this way, the ccpr2h:ccpr2l register pair effectively becomes a period register for timer3. if timer3 is running in asynchronous counter mode, the reset operation may not work. in the event that a write to timer3 coincides with a special event trigger from a ccp module, the write will take precedence. table 14-1: registers associated with timer3 as a timer/counter note: the special event triggers from the ccp2 module will not set the tmr3if interrupt flag bit (pir1<0>). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir2 oscfif cmif ? ? bclif hlvdif tmr3if ccp2if 59 pie2 oscfie cmie ? ? bclie hlvdie tmr3ie ccp2ie 59 ipr2 oscfip cmip ? ? bclip hlvdip tmr3ip ccp2ip 59 tmr3l holding register for the least significant byte of the 16-bit tmr3 register 59 tmr3h holding register for the most significant byte of the 16-bit tmr3 register 59 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 58 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer3 module.
pic18f6310/6410/8310/8410 ds39635a-page 158 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 159 pic18f6310/6410/8310/8410 15.0 capture/compare/pwm (ccp) modules pic18f6310/6410/8310/8410 devices have three ccp (capture/compare/pwm) modules, labelled ccp1, ccp2 and ccp3. all modules implement standard capture, compare and pulse-width modulation (pwm) modes. each ccp module contains a 16-bit register which can operate as a 16-bit capture register, a 16-bit compare register or a pwm master/slave duty cycle register. for the sake of clarity, all ccp module operation in the following sections is described with respect to ccp2, but are equally applicable to ccp1 and ccp3. register 15-1: ccpxcon: ccp1/ccp2/ccp3 control register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dcxb1:dcxb0 : pwm duty cycle bit 1 and bit 0 for ccp module x capture mode: unused. compare mode : unused. pwm mode: these bits are the two least significant bits (bit 1 and bit 0) of the 10-bit pwm duty cycle register. the eight most significant bits (dcx9:dcx2) of the pwm duty cycle are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccp module x mode select bits 0000 = capture/compare/pwm disabled (resets ccpx module) 0001 = reserved 0010 = compare mode, toggle output on match (ccpxif bit is set) 0011 = reserved 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode: initialize ccp pin low; on compare match, force ccp pin high (ccpif bit is set) 1001 = compare mode: initialize ccp pin high; on compare match, force ccp pin low (ccpif bit is set) 1010 = compare mode: generate software interrupt on compare match (ccpif bit is set, ccp pin reflects i/o state) 1011 = compare mode: trigger special event, reset timer, start a/d conversion on ccp2 match (ccpif bit is set) (1,2) 11xx =pwm mode note 1: the special event trigger on ccp1 will reset the timer but not start an a/d conversion on a ccp1 match. 2: for ccp3, the special event trigger is not available. this mode functions the same as compare generate interrupt mode (ccp3m3:ccp3m0 = 1010 ). legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 160 preliminary ? 2004 microchip technology inc. 15.1 ccp module configuration each capture/compare/pwm module is associated with a control register (generically, ccpxcon) and a data register (ccprx). the data register, in turn, is comprised of two 8-bit registers: ccprxl (low byte) and ccprxh (high byte). all registers are both readable and writable. 15.1.1 ccp modules and timer resources the ccp modules utilize timers 1, 2 or 3, depending on the mode selected. timer1 and timer3 are available to modules in capture or compare modes, while timer2 is available for modules in pwm mode. table 15-1: ccp mode ? timer resource the assignment of a particular timer to a module is determined by the timer-to-ccp enable bits in the t3con register (register 14-1). all three modules may be active at any given time and may share the same timer resource if they are configured to operate in the same mode (capture/compare or pwm) at the same time. depending on the configuration selected, up to three timers may be active at once, with modules in the same configuration (capture/compare or pwm) sharing timer resources. the possible configurations are shown in figure 15-1. 15.1.2 ccp2 pin assignment the ccp2mx configuration bit determines if ccp2 is multiplexed to its default or alternate assignment. by default, ccp2 is assigned to rc1 (ccp2mx = 1 ). if ccp2mx is cleared, ccp2 is multiplexed with either re7 or rb3 (re7 is the only alternative assignment for 64-pin devices). for any device in microcontroller mode, the alternate ccp2 assignment is re7. for 80-pin devices in microcprocessor, extended microcontroller or microcon- troller with boot block mode, the alternate assignment is rb3. note that re7 is the only alternative assignment for 64-pin devices. changing the pin assignment of ccp2 does not auto- matically change any requirements for configuring the port pin. users must always verify that the appropriate tris register is configured correctly for ccp2 operation, regardless of where it is located. figure 15-1: ccp and timer interconnect configurations ccp mode timer resource capture compare pwm timer1 or timer3 timer1 or timer3 timer2 timer1 is used for all capture and compare operations for all three ccp modules. timer2 is used for pwm oper- ations for all three ccp modules. timer3 is not used. all modules may share timer1 and timer2 resources as common time bases. timer1 is used for capture and compare operations for ccp1 and timer 3 is used for ccp2 and ccp3. all three modules share timer2 as a common time base for pwm operation. timer3 is used for all capture and compare operations for all three ccp modules. timer2 is used for pwm oper- ations for all three ccp modules. timer1 is not used. all modules may share timer2 and timer3 resources as common time bases. tmr1 tmr2 tmr3 ccp3 ccp2 ccp1 tmr1 tmr2 tmr3 ccp3 ccp2 ccp1 tmr1 tmr2 tmr3 ccp3 ccp2 ccp1 tmr1 tmr3 tmr2 ccp3 ccp2 ccp1 t3ccp2:tccp1 = 00 t3ccp2:tccp1 = 01 t3ccp2:tccp1 = 10 t3ccp2:tccp1 = 11 timer1 is used for capture and compare operations for ccp1 and ccp2. timer 3 is used for ccp3. all three modules share timer2 as a common time base for pwm operation.
? 2004 microchip technology inc. preliminary ds39635a-page 161 pic18f6310/6410/8310/8410 15.2 capture mode in capture mode, the ccpr2h:ccpr2l register pair captures the 16-bit value of the tmr1 or tmr3 registers when an event occurs on the ccp2 pin (rc1 or re7, depending on device configuration). an event is defined as one of the following: every falling edge every rising edge every 4th rising edge every 16th rising edge the event is selected by the mode select bits, ccp2m3:ccp2m0 (ccp2con<3:0>). when a cap- ture is made, the interrupt request flag bit, ccp2if (pir2<1>), is set; it must be cleared in software. if another capture occurs before the value in register ccpr2 is read, the old captured value is overwritten by the new captured value. 15.2.1 ccp pin configuration in capture mode, the appropriate ccpx pin should be configured as an input by setting the corresponding tris direction bit. 15.2.2 timer1/timer3 mode selection the timers that are to be used with the capture feature (timer1 and/or timer3) must be running in timer mode or synchronized counter mode. in asynchronous counter mode, the capture operation may not work. the timer to be used with each ccp module is selected in the t3con register (see section 15.1.1 ?ccp modules and timer resources? ). figure 15-2: capture mode operat ion block diagram note: if rc1/ccp2 or re7/ccp2 is configured as an output, a write to the port can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set ccp1if tmr3 enable q1:q4 ccp1con<3:0> ccp1 pin prescaler 1, 4, 16 and edge detect tmr1 enable t3ccp2 t3ccp2 ccpr2h ccpr2l tmr1h tmr1l set ccp2if tmr3 enable ccp2con<3:0> ccp2 pin prescaler 1, 4, 16 tmr3h tmr3l tmr1 enable tmr3h tmr3l and edge detect 4 4 4 q1:q4 ccpr3h ccpr3l tmr1h tmr1l set ccp3if tmr3 enable ccp3con<3:0> ccp3 pin prescaler 1, 4, 16 tmr3h tmr3l tmr1 enable t3ccp2 t3ccp1 t3ccp2 t3ccp1 and edge detect 4 4 t3ccp1 t3ccp1
pic18f6310/6410/8310/8410 ds39635a-page 162 preliminary ? 2004 microchip technology inc. 15.2.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp2ie (pie2<1>) clear to avoid false interrupts and should clear the flag bit, ccp2if, following any such change in operating mode. 15.2.4 ccp prescaler there are four prescaler settings in capture mode; they are specified as part of the operating mode selected by the mode select bits (ccp2m3:ccp2m0). whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 15-1 shows the recommended method for switching between capture prescalers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 15-1: changing between capture prescalers 15.3 compare mode in compare mode, the 16-bit ccpr2 register value is constantly compared against either the tmr1 or tmr3 register pair value. when a match occurs, the ccp2 pin can be: driven high driven low toggled (high-to-low or low-to-high) remain unchanged (that is, reflects the state of the i/o latch) the action on the pin is based on the value of the mode select bits (ccp2m3:ccp2m0). at the same time, the interrupt flag bit, ccp2if, is set. 15.3.1 ccp pin configuration the user must configure the ccpx pin as an output by clearing the appropriate tris bit. 15.3.2 timer1/timer3 mode selection timer1 and/or timer3 must be running in timer mode, or synchronized counter mode, if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 15.3.3 software interrupt mode when the generate software interrupt mode is chosen (ccp2m3:ccp2m0 = 1010 ), the ccp2 pin is not affected. only a ccp interrupt is generated if enabled and the ccp2ie bit is set. 15.3.4 special event triggers ccp1 and ccp2 are both equipped with a special event trigger. this is an internal hardware signal, generated in compare mode, to trigger actions by other modules. the special event trigger is enabled by selecting the compare special event trigger mode (ccp2m3:ccp2m0 = 1011 ). for either ccp module, the special event trigger resets the timer register pair for whichever timer resource is currently assigned as the module?s time base. this allows the ccprx registers to serve as a programmable period register for either timer. the special event trigger for ccp2 can also start an a/d conversion. in order to do this, the a/d converter must already be enabled. ccp3 is not equipped with a special event trigger. selecting the compare special event trigger mode for this device (ccp3m3:ccp3m0 = 1011 ) is functionally the same as selecting the generate software interrupt mode (ccp3m3:ccp3m0 = 1010 ). clrf ccp2con ; turn ccp module off movlw new_capt_ps ; load wreg with the ; new prescaler mode ; value and ccp on movwf ccp2con ; load ccp2con with ; this value note: clearing the ccp2con register will force the rc1 or re7 compare output latch (depending on device configuration) to the default low level. this is not the portc or porte i/o data latch. note: the special event trigger of ccp1 only resets timer1/timer3 and cannot start an a/d conversion even when the a/d converter is enabled.
? 2004 microchip technology inc. preliminary ds39635a-page 163 pic18f6310/6410/8310/8410 figure 15-3: compare mode operat ion block diagram ccpr1h ccpr1l comparator q s r output logic special event trigger set ccp1if ccp1 pin tris ccp1con<3:0> output enable ccpr2h ccpr2l comparator t3ccp2 t3ccp1 set ccp2if compare 4 (timer1/timer3 reset) q s r output logic special event trigger ccp2 pin tris ccp2con<3:0> output enable 4 (timer1/timer3 reset, a/d trigger) match compare match ccpr3h ccpr3l comparator set ccp3if q s r output logic ccp3 pin tris ccp3con<3:0> output enable 4 compare match tmr3l tmr3h tmr1l tmr1h 1 0 1 0 t3ccp2 t3ccp1 1 0
pic18f6310/6410/8310/8410 ds39635a-page 164 preliminary ? 2004 microchip technology inc. table 15-2: registers associated with capture, compare, timer1 and timer3 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 rcon ipen sboren ? ri to pd por bor 58 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 pir2 oscfif cmif ? ? bclif hlvdif tmr3if ccp2if 59 pie2 oscfie cmie ? ? bclie hlvdie tmr3ie ccp2ie 59 ipr2 oscfip cmip ? ? bclip hlvdip tmr3ip ccp2ip 59 pir3 ? ? rc2if tx2if ? ? ? ccp3if 59 pie3 ? ? rc2ie tx2ie ? ? ? ccp3ie 59 ipr3 ? ? rc2ip tx2ip ? ? ? ccp3ip 59 trisb portb data direction register 60 trisc portc data direction register 60 trise porte data direction register 60 tmr1l holding register for the least significant byte of the 16-bit tmr1 register 58 tmr1h holding register for the most significant byte of the 16-bit tmr1 register 58 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 58 tmr3h timer3 register high byte 59 tmr3l timer3 register low byte 59 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 59 ccpr1l capture/compare/pwm register 1 (lsb) 59 ccpr1h capture/compare/pwm register 1 (msb) 59 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 59 ccpr2l capture/compare/pwm register 2 (lsb) 59 ccpr2h capture/compare/pwm register 2 (msb) 59 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 59 ccpr3l capture/compare/pwm register 3 (lsb) 59 ccpr3h capture/compare/pwm register 3 (msb) 59 ccp3con ? ? dc3b1 dc3b0 ccp3m3 ccp3m2 ccp3m1 ccp3m0 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by capture/compare, timer1 or timer3. note 1: these bits are unimplemented on 64-pin devices; always maintain these bits clear.
? 2004 microchip technology inc. preliminary ds39635a-page 165 pic18f6310/6410/8310/8410 15.4 pwm mode in pulse-width modulation (pwm) mode, the ccp2 pin produces up to a 10-bit resolution pwm output. since the ccp2 pin is multiplexed with a portc or porte data latch, the appropriate tris bit must be cleared to make the ccp2 pin an output. figure 15-4 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 15.4.3 ?setup for pwm operation? . figure 15-4: simplified pwm block diagram a pwm output (figure 15-5) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 15-5: pwm output 15.4.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the following formula: equation 15-1: pwm frequency is defined as 1/[pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the ccp2 pin is set (exception: if pwm duty cycle = 0%, the ccp2 pin will not be set) the pwm duty cycle is latched from ccpr2l into ccpr2h note: clearing the ccp2con register will force the rc1 or re7 output latch (depending on device configuration) to the default low level. this is not the portc or porte i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1 note 1: the 8-bit tmr2 value is concatenated with the 2-bit internal q clock, or 2 bits of the prescaler, to create the 10-bit time base. note: the timer2 postscalers (see section 13.0 ?timer2 module? ) are not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 pwm period = (pr2) + 1] 4 t osc (tmr2 prescale value)
pic18f6310/6410/8310/8410 ds39635a-page 166 preliminary ? 2004 microchip technology inc. 15.4.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr2l register and to the ccp2con<5:4> bits. up to 10-bit resolution is available. the ccpr2l contains the eight msbs and the ccp2con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr2l:ccp2con<5:4>. the following equation is used to calculate the pwm duty cycle in time: equation 15-2: ccpr2l and ccp2con<5:4> can be written to at any time, but the duty cycle value is not latched into ccpr2h until after a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr2h is a read-only register. the ccpr2h register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm operation. when the ccpr2h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the ccp2 pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the equation: equation 15-3: 15.4.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr2l register and ccp2con<5:4> bits. 3. make the ccp2 pin an output by clearing the appropriate tris bit. 4. set the tmr2 prescale value, then enable timer2 by writing to t2con. 5. configure the ccp2 module for pwm operation. table 15-3: example pwm frequencies and resolutions at 40 mhz pwm duty cycle = (ccpr2l:ccp2con<5:4>) t osc (tmr2 prescale value) note: if the pwm duty cycle value is longer than the pwm period, the ccp2 pin will not be cleared. f osc f pwm --------------- ?? ?? log 2 () log ----------------------------- b i t s = pwm resolution (max) pwm frequency 2.44 khz 9.77 khz 39.06 khz 156.25 khz 312.50 khz 416.67 khz timer prescaler (1, 4, 16)1641111 pr2 value ffh ffh ffh 3fh 1fh 17h maximum resolution (bits) 14 12 10 8 7 6.58
? 2004 microchip technology inc. preliminary ds39635a-page 167 pic18f6310/6410/8310/8410 table 15-4: registers associated with pwm and timer2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 rcon ipen sboren ? ri to pd por bor 58 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 trisb portb data direction register 60 trisc portc data direction register 60 trise porte data direction register 60 tmr2 timer2 module register 58 pr2 timer2 module period register 58 t2con ? t2outps3 t2outps2 t2outps1 t2o utps0 tmr2on t2ckps1 t2ckps0 58 ccpr1l capture/compare/pwm register 1 (lsb) 59 ccpr1h capture/compare/pwm register 1 (msb) 59 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 59 ccpr2l capture/compare/pwm register 2 (lsb) 59 ccpr2h capture/compare/pwm register 2 (msb) 59 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 59 ccpr3l capture/compare/pwm register 3 (lsb) 59 ccpr3h capture/compare/pwm register3 (msb) 59 ccp3con ? ? dc3b1 dc3b0 ccp3m3 ccp3m2 ccp3m1 ccp3m0 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by pwm or timer2.
pic18f6310/6410/8310/8410 ds39635a-page 168 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 169 pic18f6310/6410/8310/8410 16.0 master synchronous serial port (mssp) module 16.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the mssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) - full master mode - slave mode (with general address call) the i 2 c interface supports the following modes in hardware: master mode multi-master mode slave mode 16.2 control registers the mssp module has three associated registers. these include a status register (sspstat) and two control registers (sspcon1 and sspcon2). the use of these registers and their individual configuration bits differ significantly depending on whether the mssp module is operated in spi or i 2 c mode. additional details are provided under the individual sections. 16.3 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. all four modes of spi are supported. to accomplish communication, typically three pins are used: serial data out (sdo) ? rc5/sdo serial data in (sdi) ? rc4/sdi/sda serial clock (sck) ? rc3/sck/scl additionally, a fourth pin may be used when in a slave mode of operation: slave select (ss ) ? rf7/ss figure 16-1 shows the block diagram of the mssp module when operating in spi mode. figure 16-1: mssp block diagram (spi? mode) ( ) read write internal data bus sspsr reg sspm3:sspm0 bit 0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr tris bit 2 smp:cke rc5/sdo sspbuf reg rc4/sdi/sda rf7/ss rc3/sck/ scl
pic18f6310/6410/8310/8410 ds39635a-page 170 preliminary ? 2004 microchip technology inc. 16.3.1 registers the mssp module has four registers for spi mode operation. these are: mssp control register 1 (sspcon1) mssp status register (sspstat) serial receive/transmit buffer register (sspbuf) mssp shift register (sspsr) ? not directly accessible sspcon1 and sspstat are the control and status registers in spi mode operation. the sspcon1 register is readable and writable. the lower 6 bits of the sspstat are read-only. the upper 2 bits of the sspstat are read/write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double- buffered. a write to sspbuf will write to both sspbuf and sspsr. register 16-1: sspstat: mssp status register (spi mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode. bit 6 cke: spi clock edge select bit when ckp = 0 : 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck when ckp = 1 : 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5 d/a : data/address bit used in i 2 c mode only. bit 4 p: stop bit used in i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared. bit 3 s: start bit used in i 2 c mode only. bit 2 r/w : read/write bit information used in i 2 c mode only. bit 1 ua: update address bit used in i 2 c mode only. bit 0 bf: buffer full status bit (receive mode only) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39635a-page 171 pic18f6310/6410/8310/8410 register 16-2: sspcon1: mssp control register 1 (spi mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit (transmit mode only) 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit spi slave mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. the user must read the sspbuf, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = no overflow note: in master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by writing to the sspbuf register. bit 5 sspen: synchronous serial port enable bit 1 = enables serial port and configures sck, sdo, sdi and ss as serial port pins 0 = disables serial port and configures these pins as i/o port pins note: when enabled, these pins must be properly configured as input or output. bit 4 ckp: clock polarity select bit 1 = idle state for clock is a high level 0 = idle state for clock is a low level bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 0101 = spi slave mode, clock = sck pin, ss pin control disabled, ss can be used as i/o pin 0100 = spi slave mode, clock = sck pin, ss pin control enabled 0011 = spi master mode, clock = tmr2 output/2 0010 = spi master mode, clock = f osc /64 0001 = spi master mode, clock = f osc /16 0000 = spi master mode, clock = f osc /4 note: bit combinations not specifically listed here are either reserved or implemented in i 2 c mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 172 preliminary ? 2004 microchip technology inc. 16.3.2 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon1<5:0> and sspstat<7:6>). these control bits allow the following to be specified: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) data input sample phase (middle or end of data output time) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) the mssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspbuf register. then, the buffer full detect bit, bf (sspstat<0>) and the interrupt flag bit, sspif, are set. this double-buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored and the write collision detect bit, wcol (sspcon1<7>), will be set. user software must clear the wcol bit so that it can be determined if the follow- ing write(s) to the sspbuf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. the buffer full bit, bf (sspstat<0>), indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has completed. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 16-1 shows the loading of the sspbuf (sspsr) for data transmission. the sspsr is not directly readable or writable and can only be accessed by addressing the sspbuf register. additionally, the mssp status register (sspstat) indicates the various status conditions. example 16-1: loading the sspbuf (sspsr) register loop btfss sspstat, bf ;has data been received (transmit complete)? bra loop ;no movf sspbuf, w ;wreg reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit
? 2004 microchip technology inc. preliminary ds39635a-page 173 pic18f6310/6410/8310/8410 16.3.3 enabling spi i/o to enable the serial port, ssp enable bit, sspen (sspcon1<5>), must be set. to reset or reconfigure spi mode, clear the sspen bit, reinitialize the sspcon registers and then set the sspen bit. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port func- tion, some must have their data direction bits (in the tris register) appropriately programmed as follows: sdi is automatically controlled by the spi module sdo must have trisc<5> bit cleared sck (master mode) must have trisc<3> bit cleared sck (slave mode) must have trisc<3> bit set ss must have trisf<7> bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. 16.3.4 typical connection figure 16-2 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sck signal. data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock. both processors should be programmed to the same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: master sends data ? slave sends dummy data master sends data ? slave sends data master sends dummy data ? slave sends data figure 16-2: spi? master/slave connection serial input buffer (sspbuf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm3:sspm0 = 00xxb serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm3:sspm0 = 010xb serial clock
pic18f6310/6410/8310/8410 ds39635a-page 174 preliminary ? 2004 microchip technology inc. 16.3.5 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 16-2) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be dis- abled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?line activity monitor? mode. the clock polarity is selected by appropriately programming the ckp bit (sspcon1<4>). this then, would give waveforms for spi communication as shown in figure 16-3, figure 16-5 and figure 16-6, where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: f osc /4 (or t cy ) f osc /16 (or 4 t cy ) f osc /64 (or 16 t cy ) timer2 output/2 this allows a maximum data rate (at 40 mhz) of 10.00 mbps. figure 16-3 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 16-3: spi? mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 sdi sspif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) next q4 cycle after q2 bit 0
? 2004 microchip technology inc. preliminary ds39635a-page 175 pic18f6310/6410/8310/8410 16.3.6 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received, the device will wake-up from sleep. 16.3.7 slave select synchronization the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon1<3:0> = 04h). the pin must not be driven low for the ss pin to function as an input. the data latch must be high. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable, depending on the application. when the spi module resets, the bit counter is forced to ? 0 ?. this can be done by either forcing the ss pin to a high level or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver, the sdo pin can be configured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus conflict. figure 16-4: slave synchronization waveform note 1: when the spi is in slave mode with ss pin control enabled (sspcon<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: if the spi is used in slave mode with cke set, then the ss pin control must be enabled. sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag bit 0 bit 7 bit 0 next q4 cycle after q2
pic18f6310/6410/8310/8410 ds39635a-page 176 preliminary ? 2004 microchip technology inc. figure 16-5: spi? mode waveform (slave mode with cke = 0 ) figure 16-6: spi? mode waveform (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag optional next q4 cycle after q2 bit 0 sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 1 ) cke = 1 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag not optional next q4 cycle after q2
? 2004 microchip technology inc. preliminary ds39635a-page 177 pic18f6310/6410/8310/8410 16.3.8 sleep operation in spi master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the sleep mode, all clocks are halted. in most power managed modes, a clock is provided to the peripherals. that clock should be from the primary clock source, the secondary clock (timer1 oscillator at 32.768 khz) or the intosc source. see section 2.7 ?clock sources and oscillator switching? for additional information. in most cases, the speed that the master clocks spi data is not important; however, this should be evaluated for each system. if mssp interrupts are enabled, they can wake the con- troller from sleep mode, or one of the idle modes, when the master completes sending data. if an exit from sleep or idle mode is not desired, mssp interrupts should be disabled. if the sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the devices wakes. after the device returns to run mode, the module will resume transmitting and receiving data. in spi slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in any power managed mode and data to be shifted into the spi transmit/ receive shift register. when all 8 bits have been received, the mssp interrupt flag bit will be set and if enabled, will wake the device. 16.3.9 effects of a reset a reset disables the mssp module and terminates the current transfer. 16.3.10 bus mode compatibility table 16-1 shows the compatibility between the standard spi modes and the states of the ckp and cke control bits. table 16-1: spi? bus modes there is also an smp bit which controls when the data is sampled. table 16-2: registers associated with spi? operation standard spi mode terminology control bits state ckp cke 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 trisc portc data direction register 60 trisf portf data direction register 60 sspbuf synchronous serial port receive buffer/transmit register 58 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 58 sspstat smp cke d/a p s r/w ua bf 58 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the mssp in spi mode.
pic18f6310/6410/8310/8410 ds39635a-page 178 preliminary ? 2004 microchip technology inc. 16.4 i 2 c mode the mssp module in i 2 c mode fully implements all master and slave functions (including general call support) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master function). the mssp module implements the standard mode specifications as well as 7-bit and 10-bit addressing. two pins are used for data transfer: serial clock (scl) ? rc3/sck/scl serial data (sda) ? rc4/sdi/sda the user must configure these pins as inputs through the trisc<4:3> bits. figure 16-7: mssp block diagram (i 2 c? mode) 16.4.1 registers the mssp module has six registers for i 2 c operation. these are: mssp control register 1 (sspcon1) mssp control register 2 (sspcon2) mssp status register (sspstat) serial receive/transmit buffer register (sspbuf) mssp shift register (sspsr) ? not directly accessible mssp address register (sspadd) sspcon1, sspcon2 and sspstat are the control and status registers in i 2 c mode operation. the sspcon1 and sspcon2 registers are readable and writable. the lower 6 bits of the sspstat are read-only. the upper 2 bits of the sspstat are read/write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to, or read from. sspadd register holds the slave device address when the ssp is configured in i 2 c slave mode. when the ssp is configured in master mode, the lower 7 bits of sspadd act as the baud rate generator reload value. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double- buffered. a write to sspbuf will write to both sspbuf and sspsr. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) rc3/sck/scl rc4/ shift clock msb sdi/ lsb sda
? 2004 microchip technology inc. preliminary ds39635a-page 179 pic18f6310/6410/8310/8410 register 16-3: sspstat: mssp status register (i 2 c mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a p (1) s (1) r/w (2,3) ua bf bit 7 bit 0 bit 7 smp: slew rate control bit in master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high-speed mode (400 khz) bit 6 cke: smbus select bit in master or slave mode: 1 = enable smbus specific inputs 0 = disable smbus specific inputs bit 5 d/a : data/address bit in master mode: reserved. in slave mode: 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (1) 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last bit 3 s: start bit (1) 1 = indicates that a start bit has been detected last 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) in slave mode: (2) 1 = read 0 = write in master mode: (3) 1 = transmit is in progress 0 = transmit is not in progress bit 1 ua: update address bit (10-bit slave mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit in transmit mode: 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty in receive mode: 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty note 1: this bit is cleared on reset and when sspen is cleared. 2: this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit or not ack bit. 3: oring this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in idle mode. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 180 preliminary ? 2004 microchip technology inc. register 16-4: sspcon1: mssp control register 1 (i 2 c mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen (1) ckp sspm3 (2) sspm2 (2) sspm1 (2) sspm0 (2) bit 7 bit 0 bit 7 wcol: write collision detect bit in master transmit mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started (must be cleared in software) 0 = no collision in slave transmit mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision in receive mode (master or slave modes): this is a ?don?t care? bit. bit 6 sspov: receive overflow indicator bit in receive mode: 1 = a byte is received while the sspbuf register is still holding the previous byte (must be cleared in software) 0 = no overflow in transmit mode: this is a ?don?t care? bit in transmit mode. bit 5 sspen: synchronous serial port enable bit (1) 1 = enables the serial port and configures the sda and scl pins as the serial port pins 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: sck release control bit in slave mode: 1 = releases clock 0 = holds clock low (clock stretch), used to ensure data setup time in master mode: unused in this mode. bit 3-0 sspm3:sspm0: synchronous serial port mode select bits (2) 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1011 = i 2 c firmware controlled master mode (slave idle) 1000 = i 2 c master mode, clock = f osc /(4 * (sspadd + 1)) 0111 = i 2 c slave mode, 10-bit address 0110 = i 2 c slave mode, 7-bit address note 1: when enabled, the sda and scl pins must be properly configured as input or output. 2: bit combinations not specifically listed here are either reserved or implemented in spi mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39635a-page 181 pic18f6310/6410/8310/8410 register 16-5: sspcon2: mssp control register 2 (i 2 c mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt (1) acken (2) rcen (2) pen (2) rsen (2) sen (2) bit 7 bit 0 bit 7 gcen: general call enable bit (slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (master transmit mode only) 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt: acknowledge data bit (master receive mode only) (1) 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (master receive mode only) (2) 1 = initiate acknowledge sequence on sda and scl pins and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (master mode only) (2) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (master mode only) (2) 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enable bit (master mode only) (2) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enable/stretch enable bit (2) in master mode: 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note 1: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. 2: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled). legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 182 preliminary ? 2004 microchip technology inc. 16.4.2 operation the mssp module functions are enabled by setting mssp enable bit, sspen (sspcon<5>). the sspcon1 register allows control of the i 2 c operation. four mode selection bits (sspcon<3:0>) allow one of the following i 2 c modes to be selected: i 2 c master mode, clock = (f osc /4) x (sspadd + 1) i 2 c slave mode (7-bit address) i 2 c slave mode (10-bit address) i 2 c slave mode (7-bit address) with start and stop bit interrupts enabled i 2 c slave mode (10-bit address) with start and stop bit interrupts enabled i 2 c firmware controlled master mode, slave is idle selection of any i 2 c mode with the sspen bit set, forces the scl and sda pins to be open-drain, provided these pins are programmed to inputs by setting the appropriate trisc bits. to ensure proper operation of the module, pull-up resistors must be provided externally to the scl and sda pins. 16.4.3 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the mssp module will override the input state with the output data when required (slave-transmitter). the i 2 c slave mode hardware will always generate an interrupt on an address match. through the mode select bits, the user can also choose to interrupt on start and stop bits when an address is matched, or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse and load the sspbuf register with the received value currently in the sspsr register. any combination of the following conditions will cause the mssp module not to give this ack pulse: the buffer full bit, bf (sspstat<0>), was set before the transfer was received. the overflow bit, sspov (sspcon<6>), was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf, but bit sspif (pir1<3>) is set. the bf bit is cleared by reading the sspbuf register, while bit sspov is cleared through software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, are shown in timing parameter #100 and parameter #101. 16.4.3.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8 bits are shifted into the sspsr register. all incom- ing bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is compared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match and the bf and sspov bits are clear, the following events occur: 1. the sspsr register value is loaded into the sspbuf register. 2. the buffer full bit, bf, is set. 3. an ack pulse is generated. 4. mssp interrupt flag bit, sspif (pir1<3>), is set (interrupt is generated, if enabled) on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ? 11110 a9 a8 0 ?, where ? a9 ? and ? a8 ? are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. receive first (high) byte of address (bits sspif, bf and ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf and ua are set). 5. update the sspadd register with the first (high) byte of address. if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif.
? 2004 microchip technology inc. preliminary ds39635a-page 183 pic18f6310/6410/8310/8410 16.4.3.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register and the sda line is held low (ack ). when the address byte overflow condition exists, then the no acknowledge (ack ) pulse is given. an overflow condition is defined as either bit bf (sspstat<0>) is set, or bit sspov (sspcon1<6>) is set. an mssp interrupt is generated for each data transfer byte. flag bit sspif (pir1<3>) must be cleared in software. the sspstat register is used to determine the status of the byte. if sen is enabled (sspcon2<0> = 1 ), rc3/sck/scl will be held low (clock stretch) following each data transfer. the clock must be released by setting bit ckp (sspcon<4>). see section 16.4.4 ?clock stretching? for more detail. 16.4.3.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit and pin rc3/sck/scl is held low regardless of sen (see section 16.4.4 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspbuf register which also loads the sspsr register. then, pin rc3/ sck/scl should be enabled by setting bit ckp (sspcon1<4>). the 8 data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 16-9). the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line is high (not ack ), then the data transfer is complete. in this case, when the ack is latched by the slave, the slave logic is reset (resets sspstat regis- ter) and the slave monitors for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the sspbuf register. again, pin rc3/sck/scl must be enabled by setting bit ckp. an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared in software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse.
pic18f6310/6410/8310/8410 ds39635a-page 184 preliminary ? 2004 microchip technology inc. figure 16-8: i 2 c? slave mode timing with sen = 0 (reception, 7-bit address) sda scl sspif bf (sspstat<0>) sspov (sspcon1<6>) s 1 2 3 4 56 7 8 91 2 3 4 5 67 89 1 2 3 4 5 7 8 9 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 (pir1<3>) ckp (ckp does not reset to ? 0 ? when sen = 0 )
? 2004 microchip technology inc. preliminary ds39635a-page 185 pic18f6310/6410/8310/8410 figure 16-9: i 2 c? slave mode timing (transmission, 7-bit address) sda scl sspif (pir1<3>) bf (sspstat<0>) a6 a5 a4 a3 a2 a1 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software from sspif isr data in sampled s ack transmitting data r/w = 1 ack receiving address a7 d7 9 1 d6 d5 d4 d3 d2 d1 d0 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software from sspif isr transmitting data d7 1 ckp p ack ckp is set in software ckp is set in software scl held low while cpu responds to sspif
pic18f6310/6410/8310/8410 ds39635a-page 186 preliminary ? 2004 microchip technology inc. figure 16-10: i 2 c? slave mode timing with sen = 0 (reception, 10-bit address) sda scl sspif bf (sspstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 d7 d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 (pir1<3>) cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) sspov is set because sspbuf is still full. ack is not sent. (ckp does not reset to ? 0 ? when sen = 0 ) clock is held low until update of sspadd has taken place
? 2004 microchip technology inc. preliminary ds39635a-page 187 pic18f6310/6410/8310/8410 figure 16-11: i 2 c? slave mode timing (transmission, 10-bit address) sda scl sspif bf (sspstat<0>) s 1234 5 6789 1 2345 678 9 12345 78 9 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1a0 1 1 1 1 0 a8 r/w = 1 ack ack r/w = 0 ack receive first byte of address cleared in software bus master terminates transfer a9 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address. sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf flag sr cleared in software write of sspbuf initiates transmit cleared in software completion of clears bf flag ckp (sspcon1<4>) ckp is set in software ckp is automatically cleared in hardware, holding scl low clock is held low until update of sspadd has taken place data transmission clock is held low until ckp is set to ? 1 ? third address sequence bf flag is clear at the end of the
pic18f6310/6410/8310/8410 ds39635a-page 188 preliminary ? 2004 microchip technology inc. 16.4.4 clock stretching both 7 and 10-bit slave modes implement automatic clock stretching during a transmit sequence. the sen bit (sspcon2<0>) allows clock stretching to be enabled during receives. setting sen will cause the scl pin to be held low at the end of each data receive sequence. 16.4.4.1 clock stretching for 7-bit slave receive mode (sen = 1 ) in 7-bit slave receive mode, on the falling edge of the ninth clock at the end of the ack sequence, if the bf bit is set, the ckp bit in the sspcon1 register is automatically cleared, forcing the scl output to be held low. the ckp being cleared to ? 0 ? will assert the scl line low. the ckp bit must be set in the user?s isr before reception is allowed to continue. by holding the scl line low, the user has time to service the isr and read the contents of the sspbuf before the master device can initiate another receive sequence. this will prevent buffer overruns from occurring (see figure 16-13). 16.4.4.2 clock stretching for 10-bit slave receive mode (sen = 1 ) in 10-bit slave receive mode during the address sequence, clock stretching automatically takes place but ckp is not cleared. during this time, if the ua bit is set after the ninth clock, clock stretching is initiated. the ua bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the r/w bit cleared to ? 0 ?. the release of the clock line occurs upon updating sspadd. clock stretching will occur on each data receive sequence as described in 7-bit mode. 16.4.4.3 clock stretching for 7-bit slave transmit mode 7-bit slave transmit mode implements clock stretching by clearing the ckp bit after the falling edge of the ninth clock, if the bf bit is clear. this occurs regardless of the state of the sen bit. the user?s isr must set the ckp bit before transmis- sion is allowed to continue. by holding the scl line low, the user has time to service the isr and load the contents of the sspbuf before the master device can initiate another transmit sequence (see figure 16-9). 16.4.4.4 clock stretching for 10-bit slave transmit mode in 10-bit slave transmit mode, clock stretching is controlled during the first two address sequences by the state of the ua bit, just as it is in 10-bit slave receive mode. the first two addresses are followed by a third address sequence which contains the high- order bits of the 10-bit address and the r/w bit set to ? 1 ?. after the third address sequence is performed, the ua bit is not set, the module is now configured in transmit mode and clock stretching is controlled by the bf flag as in 7-bit slave transmit mode (see figure 16-11). note 1: if the user reads the contents of the sspbuf before the falling edge of the ninth clock, thus clearing the bf bit, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit. the user should be careful to clear the bf bit in the isr before the next receive sequence in order to prevent an overflow condition. note: if the user polls the ua bit and clears it by updating the sspadd register before the falling edge of the ninth clock occurs and if the user hasn?t cleared the bf bit by read- ing the sspbuf register before that time, then the ckp bit will still not be asserted low. clock stretching on the basis of the state of the bf bit only occurs during a data sequence, not an address sequence. note 1: if the user loads the contents of sspbuf, setting the bf bit before the falling edge of the ninth clock, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit.
? 2004 microchip technology inc. preliminary ds39635a-page 189 pic18f6310/6410/8310/8410 16.4.4.5 clock synchronization and the ckp bit when the ckp bit is cleared, the scl output is forced to ? 0 ?. however, setting the ckp bit will not assert the scl output low until the scl output is already sam- pled low. therefore, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have deasserted scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 16-12). figure 16-12: clock synchronization timing sda scl dx ? 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspcon ckp master device deasserts clock master device asserts clock
pic18f6310/6410/8310/8410 ds39635a-page 190 preliminary ? 2004 microchip technology inc. figure 16-13: i 2 c? slave mode timing with sen = 1 (reception, 7-bit address) sda scl sspif bf (sspstat<0>) sspov (sspcon1<6>) s 1 234 567 89 1 2345 67 89 1 23 45 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 (pir1<3>) ckp ckp written to ? 1 ? in if bf is cleared prior to the falling edge of the 9th clock, ckp will not be reset to ? 0 ? and no clock stretching will occur software clock is held low until ckp is set to ? 1 ? clock is not held low because buffer full bit is clear prior to falling edge of 9th clock clock is not held low because ack = 1 bf is set after falling edge of the 9th clock, ckp is reset to ? 0 ? and clock stretching occurs
? 2004 microchip technology inc. preliminary ds39635a-page 191 pic18f6310/6410/8310/8410 figure 16-14: i 2 c? slave mode timing sen = 1 (reception, 10-bit address) sda scl sspif bf (sspstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 d7d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 (pir1<3>) cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address after falling edge ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address after falling edge sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) ckp written to ? 1 ? note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. in software clock is held low until update of sspadd has taken place of ninth clock of ninth clock sspov is set because sspbuf is still full. ack is not sent. dummy read of sspbuf to clear bf flag clock is held low until ckp is set to ? 1 ? clock is not held low because ack = 1
pic18f6310/6410/8310/8410 ds39635a-page 192 preliminary ? 2004 microchip technology inc. 16.4.5 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all ? 0 ?s with r/w = 0 . the general call address is recognized when the gen- eral call enable bit (gcen) is enabled (sspcon2<7> set). following a start bit detect, 8 bits are shifted into the sspsr and the address is compared against the sspadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf flag bit is set (eighth bit) and on the falling edge of the ninth bit (ack bit), the sspif interrupt flag bit is set. when the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the sspbuf. the value can be used to determine if the address was device specific or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match and the ua bit is set (sspstat<1>). if the general call address is sampled when the gcen bit is set, while the slave is configured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set and the slave will begin receiving data after the acknowledge (figure 16-15). figure 16-15: slave mode general call address sequence (7 or 10-bit address mode) sda scl s sspif bf (sspstat<0>) sspov (sspcon1<6>) cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address gcen (sspcon2<7>) receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt ? 0 ? ? 1 ?
? 2004 microchip technology inc. preliminary ds39635a-page 193 pic18f6310/6410/8310/8410 16.4.6 master mode master mode is enabled by setting and clearing the appropriate sspm bits in sspcon1 and by setting the sspen bit. in master mode, the scl and sda lines are manipulated by the mssp hardware. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set or the bus is idle, with both the s and p bits clear. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit conditions. once master mode is enabled, the user has six options. 1. assert a start condition on sda and scl. 2. assert a repeated start condition on sda and scl. 3. write to the sspbuf register initiating transmission of data/address. 4. configure the i 2 c port to receive data. 5. generate an acknowledge condition at the end of a received byte of data. 6. generate a stop condition on sda and scl. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt, if enabled): start condition stop condition data transfer byte transmitted/received acknowledge transmit repeated start figure 16-16: mssp block diagram (i 2 c? master mode) note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to initiate transmission before the start condi- tion is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur. read write sspsr start bit, stop bit, sspbuf internal data bus set/reset, s, p, wcol (sspstat) shift clock msb lsb sda acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif reset ackstat, pen (sspcon2) rate generator sspm3:sspm0 start bit detect
pic18f6310/6410/8310/8410 ds39635a-page 194 preliminary ? 2004 microchip technology inc. 16.4.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address, followed by a ? 1 ? to indicate the receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmit- ted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator used for the spi mode oper- ation is used to set the scl clock frequency for either 100 khz, 400 khz or 1 mhz i 2 c operation. see section 16.4.7 ?baud rate? for more detail. a typical transmit sequence would go as follows: 1. the user generates a start condition by setting the start enable bit, sen (sspcon2<0>). 2. sspif is set. the mssp module will wait the required start time before any other operation takes place. 3. the user loads the sspbuf with the slave address to transmit. 4. address is shifted out the sda pin until all 8 bits are transmitted. 5. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 6. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 7. the user loads the sspbuf with 8 bits of data. 8. data is shifted out the sda pin until all 8 bits are transmitted. 9. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 10. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 11. the user generates a stop condition by setting the stop enable bit, pen (sspcon2<2>). 12. interrupt is generated once the stop condition is complete.
? 2004 microchip technology inc. preliminary ds39635a-page 195 pic18f6310/6410/8310/8410 16.4.7 baud rate in i 2 c master mode, the baud rate generator (brg) reload value is placed in the lower 7 bits of the sspadd register (figure 16-17). when a write occurs to sspbuf, the baud rate generator will automatically begin counting. the brg counts down to ? 0 ? and stops until another reload has taken place. the brg count is decremented twice per instruction cycle (t cy ) on the q2 and q4 clocks. in i 2 c master mode, the brg is reloaded automatically. once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ack ), the internal clock will automatically stop counting and the scl pin will remain in its last state. table 16-3 demonstrates clock rates based on instruction cycles and the brg value loaded into sspadd. figure 16-17: baud rate generator block diagram table 16-3: i 2 c? clock rate w/brg sspm3:sspm0 brg down counter clko f osc /4 sspadd<6:0> sspm3:sspm0 scl reload control reload f cy f cy *2 brg value f scl (2 rollovers of brg) 10 mhz 20 mhz 19h 400 khz (1) 10 mhz 20 mhz 20h 312.5 khz 10 mhz 20 mhz 3fh 100 khz 4 mhz 8 mhz 0ah 400 khz (1) 4 mhz 8 mhz 0dh 308 khz 4 mhz 8 mhz 28h 100 khz 1 mhz 2 mhz 03h 333 khz (1) 1 mhz 2 mhz 0ah 100 khz 1 mhz 2 mhz 00h 1 mhz (1) note 1: the i 2 c interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application.
pic18f6310/6410/8310/8410 ds39635a-page 196 preliminary ? 2004 microchip technology inc. 16.4.7.1 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, deasserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device (figure 16-18). figure 16-18: baud rate generator timing with clock arbitration sda scl scl deasserted but slave holds dx ? 1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles
? 2004 microchip technology inc. preliminary ds39635a-page 197 pic18f6310/6410/8310/8410 16.4.8 i 2 c master mode start condition timing to initiate a start condition, the user sets the start enable bit, sen (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition and causes the s bit (sspstat<3>) to be set. following this, the baud rate generator is reloaded with the contents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2<0>) will be automatically cleared by hard- ware, the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. 16.4.8.1 wcol status flag if the user writes the sspbuf when a start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 16-19: first start bit timing note: if, at the beginning of the start condition, the sda and scl pins are already sam- pled low, or if during the start condition, the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag, bclif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspstat<3>) and sets sspif bit
pic18f6310/6410/8310/8410 ds39635a-page 198 preliminary ? 2004 microchip technology inc. 16.4.9 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2<1>) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sam- pled low, the baud rate generator is loaded with the contents of sspadd<5:0> and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate genera- tor times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0 ) for one t brg while scl is high. following this, the rsen bit (sspcon2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. after the first 8 bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or 8 bi ts of data (7-bit mode). 16.4.9.1 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, the wcol is set and the con- tents of the buffer are unchanged (the write doesn?t occur). figure 16-20: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: sda is sampled low when scl goes from low-to-high. scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here falling edge of ninth clock, end of xmit at completion of start bit, hardware clears rsen bit 1st bit set s (sspstat<3>) t brg t brg sda = 1 , sda = 1 , scl (no change). scl = 1 occurs here. t brg t brg t brg and sets sspif
? 2004 microchip technology inc. preliminary ds39635a-page 199 pic18f6310/6410/8310/8410 16.4.10 i 2 c master mode transmission transmission of a data byte, a 7-bit address, or the other half of a 10-bit address is accomplished by simply writing a value to the sspbuf register. this action will set the buffer full flag bit, bf and allow the baud rate generator to begin counting and start the next trans- mission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time specification parameter #106). scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high (see data setup time specification parameter #107). when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. this allows the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurred, or if data was received properly. the status of ack is written into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged (figure 16-21). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl until all 7 address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will deassert the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspcon2<6>). following the falling edge of the ninth clock transmis- sion of the address, the sspif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 16.4.10.1 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 16.4.10.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). wcol must be cleared in software. 16.4.10.3 ackstat status flag in transmit mode, the ackstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowl- edge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 16.4.11 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high-to-low/ low-to-high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf flag bit is set, the sspif flag bit is set and the baud rate generator is suspended from counting, holding scl low. the mssp is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by set- ting the acknowledge sequence enable bit, acken (sspcon2<4>). 16.4.11.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 16.4.11.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspsr and the bf flag bit is already set from a previous reception. 16.4.11.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). note: the mssp module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded.
pic18f6310/6410/8310/8410 ds39635a-page 200 preliminary ? 2004 microchip technology inc. figure 16-21: i 2 c? master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from ssp interrupt after start condition, sen cleared by hardware s sspbuf written with 7-bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared in software sspbuf written pen cleared in software r/w
? 2004 microchip technology inc. preliminary ds39635a-page 201 pic18f6310/6410/8310/8410 figure 16-22: i 2 c? master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 123456789 12345678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1 ) write to sspbuf occurs here ack from slave master configured as a receiver by programming sspcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0 , scl = 1 while cpu (sspstat<0>) ack cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared in software sda = ackdt = 0 sspov is set because sspbuf is still full last bit is shifted into sspsr and contents are unloaded into sspbuf
pic18f6310/6410/8310/8410 ds39635a-page 202 preliminary ? 2004 microchip technology inc. 16.4.12 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode (figure 16-23). 16.4.12.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). 16.4.13 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspcon2<2>). at the end of a receive/ transmit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sam- pled low, the baud rate generator is reloaded and counts down to ? 0 ?. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sam- pled high while scl is high, the p bit (sspstat<4>) is set. a t brg later, the pen bit is cleared and the sspif bit is set (figure 16-24). 16.4.13.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 16-23: acknowledge sequence waveform figure 16-24: stop cond ition receive or transmit mode note: t brg = one baud rate generator period. sda scl set sspif at the end acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg of receive 8 acken = 1 , ackdt = 0 d0 9 sspif software set sspif at the end of acknowledge sequence cleared in software ack scl sda sda asserted low before rising edge of clock write to sspcon2, set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set
? 2004 microchip technology inc. preliminary ds39635a-page 203 pic18f6310/6410/8310/8410 16.4.14 sleep operation while in sleep mode, the i 2 c module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 16.4.15 effect of a reset a reset disables the mssp module and terminates the current transfer. 16.4.16 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat<4>) is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed in hardware with the result placed in the bclif bit. the states where arbitration can be lost are: address transfer data transfer a start condition a repeated start condition an acknowledge condition 16.4.17 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda, by letting sda float high and another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin = 0 , then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif and reset the i 2 c port to its idle state (figure 16-25). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the sspbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condi- tion was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are deas- serted and the respective control bits in the sspcon2 register are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register, or the bus is idle and the s and p bits are cleared. figure 16-25: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data doesn?t match what is driven bus collision has occurred. set bus collision interrupt (bclif) by the master. by master data changes while scl = 0
pic18f6310/6410/8310/8410 ds39635a-page 204 preliminary ? 2004 microchip technology inc. 16.4.17.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition (figure 16-26). b) scl is sampled low before sda is asserted low (figure 16-27). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: the start condition is aborted, the bclif flag is set and the mssp module is reset to its idle state (figure 16-26). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to ? 0 ?. if the scl pin is sampled low while sda is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early (figure 16-28). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to ? 0 ? and during this time, if the scl pins are sampled as ? 0 ?, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 16-26: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address follow- ing the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bclif s sspif sda = 0 , scl = 1 . sspif and bclif are cleared in software sspif and bclif are cleared in software set bclif, start condition. set bclif.
? 2004 microchip technology inc. preliminary ds39635a-page 205 pic18f6310/6410/8310/8410 figure 16-27: bus collision duri ng a start condition (scl = 0 ) figure 16-28: brg reset due to sda arbitrat ion during start condition sda scl sen bus collision occurs. set bclif. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bclif s sspif interrupt cleared in software bus collision occurs. set bclif. scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sda scl sen set s less than t brg t brg sda = 0 , scl = 1 bclif s sspif s interrupts cleared in software set sspif sda = 0 , scl = 1 , scl pulled low after brg time-out set sspif ? 0 ? sda pulled low by other master. reset brg and assert sda. set sen, enable start sequence if sda = 1 , scl = 1
pic18f6310/6410/8310/8410 ds39635a-page 206 preliminary ? 2004 microchip technology inc. 16.4.17.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data ? 1 ?. when the user deasserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0> and counts down to ? 0 ?. the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, figure 16-29). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high-to-low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition (see figure 16-30). if, at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 16-29: bus collision during a repeat ed start condition (case 1) figure 16-30: bus collision during a repe ated start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0 , set bclif and release sda and scl. cleared in software ? 0 ? ? 0 ? sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl. t brg t brg ? 0 ?
? 2004 microchip technology inc. preliminary ds39635a-page 207 pic18f6310/6410/8310/8410 16.4.17.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is deasserted, scl is sampled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd<6:0> and counts down to ? 0 ?. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? (figure 16-31). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? (figure 16-32). figure 16-31: bus collision during a stop condition (case 1) figure 16-32: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif ? 0 ? ? 0 ? sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif ? 0 ? ? 0 ?
pic18f6310/6410/8310/8410 ds39635a-page 208 preliminary ? 2004 microchip technology inc. table 16-4: registers associated with i 2 c? operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 trisc portc data direction register 60 sspbuf synchronous serial port receive buffer/transmit register 58 sspadd synchronous serial port receive buffer/transmit register 58 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 58 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 58 sspstat smp cke d/a p s r/w ua bf 58 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the mssp in spi? mode.
? 2004 microchip technology inc. preliminary ds39635a-page 209 pic18f6310/6410/8310/8410 17.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) pic18f6310/6410/8310/8410 devices have three serial i/o modules: the mssp module, discussed in the previous chapter and two universal synchronous asynchronous receiver transmitter (usart) mod- ules. (generically, the usart is also known as a serial communications interface or sci.) the usart can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as crt terminals and personal computers. it can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms, etc. there are two distinct implementations of the usart module in these devices: the enhanced usart (eusart), discussed here and the addressable usart, discussed in the next chapter. for this device family, usart1 always refers to the eusart, while usart2 is always the ausart. the eusart and ausart modules implement the same core features for serial communications; their basic operation is essentially the same. the eusart module provides additional features, including auto- matic baud rate detection and calibration, automatic wake-up on sync break reception and 12-bit break character transmit. these features make it ideally suited for use in local interconnect network bus (lin bus) systems. the eusart can be configured in the following modes: asynchronous (full-duplex) with: - auto-wake-up on character reception - auto-baud calibration - 12-bit break character transmission synchronous ? master (half-duplex) with selectable clock polarity synchronous ? slave (half-duplex) with selectable clock polarity the pins of the enhanced usart are multiplexed with portc. in order to configure rc6/tx1/ck1 and rc7/rx1/dt1 as a usart: bit spen (rcsta1<7>) must be set (= 1 ) bit trisc<7> must be set (= 1 ) bit trisc<6> must be set (= 1 ) the operation of the enhanced usart module is controlled through three registers: transmit status and control register 1 (txsta1) receive status and control register 1 (rcsta1) baud rate control register 1 (baudcon1) the registers are described in register 17-1, register 17-2 and register 17-3. note: the usart control will automatically reconfigure the pin from input to output as needed.
pic18f6310/6410/8310/8410 ds39635a-page 210 preliminary ? 2004 microchip technology inc. register 17-1: txsta1: eusart transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-1 r/w-0 csrc tx9 txen (1) sync sendb brgh trmt tx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode: don?t care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled note 1: sren/cren overrides txen in sync mode. bit 4 sync: ausart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode: 1 = send sync break on next transmission (cleared by hardware upon completion) 0 = sync break transmission completed synchronous mode: don?t care. bit 2 brgh: high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data can be address/data bit or a parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39635a-page 211 pic18f6310/6410/8310/8410 register 17-2: rcsta1: eusart receive status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : don?t care. synchronous mode ? master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave: don?t care. bit 4 cren: continuous receive enable bit asynchronous mode: 1 = enables receiver 0 = disables receiver synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection, enables interrupt and loads the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 9-bit (rx9 = 0 ) : don?t care. bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcreg register and receiving next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 212 preliminary ? 2004 microchip technology inc. register 17-3: baudcon1: baud rate control regi ster 1 r/w-0 r-1 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 abdovf rcidl ? sckp brg16 ? wue abden bit 7 bit 0 bit 7 abdovf : auto-baud acquisition rollover status bit 1 = a brg rollover has occurred during auto-baud rate detect mode (must be cleared in software) 0 = no brg rollover has occurred bit 6 rcidl : receive operation idle status bit 1 = receive operation is idle 0 = receive operation is active bit 5 unimplemented: read as ? 0 ? bit 4 sckp : synchronous clock polarity select bit asynchronous mode: unused in this mode. synchronous mode: 1 = idle state for clock (ck) is a high level 0 = idle state for clock (ck) is a low level bit 3 brg16: 16-bit baud rate register enable bit 1 = 16-bit baud rate generator ? spbrgh1 and spbrg1 0 = 8-bit baud rate generator ? spbrg1 only (compatible mode), spbrgh1 value ignored bit 2 unimplemented: read as ? 0 ? bit 1 wue: wake-up enable bit asynchronous mode: 1 = eusart will continue to sample the rx pin ? interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = rx pin not monitored or rising edge detected synchronous mode: unused in this mode. bit 0 abden : auto-baud detect enable bit asynchronous mode: 1 = enable baud rate measurement on the next character. requires reception of a sync field (55h); cleared in hardware upon completion. 0 = baud rate measurement disabled or completed synchronous mode: unused in this mode. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39635a-page 213 pic18f6310/6410/8310/8410 17.1 eusart baud rate generator (brg) the brg is a dedicated, 8-bit or 16-bit generator that supports both the asynchronous and synchronous modes of the eusart. by default, the brg operates in 8-bit mode; setting the brg16 bit (baudcon1<3>) selects 16-bit mode. the spbrgh1:spbrg1 register pair controls the period of a free running timer. in asynchronous mode, bits brgh (txsta1<2>) and brg16 (baudcon1<3>) also control the baud rate. in synchronous mode, brgh is ignored. table 17-1 shows the formula for computa- tion of the baud rate for different eusart modes that only apply in master mode (internally generated clock). given the desired baud rate and f osc , the nearest integer value for the spbrgh1:spbrg1 registers can be calculated using the formulas in table 17-1. from this, the error in baud rate can be determined. an example calculation is shown in example 17-1. typical baud rates and error values for the various asynchronous modes are shown in table 17-2. it may be advantageous to use the high baud rate (brgh = 1 ) or the 16-bit brg to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. writing a new value to the spbrgh1:spbrg1 registers causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 17.1.1 operation in power managed modes the device clock is used to generate the desired baud rate. when one of the power managed modes is entered, the new clock source may be operating at a different frequency. this may require an adjustment to the value in the spbrg1 register pair. 17.1.2 sampling the data on the rx1 pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx1 pin. table 17-1: baud rate formulas example 17-1: calculating baud rate error table 17-2: registers associated with the baud rate generator configuration bits brg/eusart mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n + 1)] 001 8-bit/asynchronous f osc /[16 (n + 1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n + 1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = don?t care, n = value of spbrgh1:spbrg1 register pair name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 59 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 59 baudcon1 abdovf rcidl ? sckp brg16 ? wue abden 60 spbrgh1 baud rate generator register, high byte 60 spbrg1 baud rate generator register, low byte 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the brg. for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit brg: desired baud rate = f osc /(64 ([spbrgh1:spbrg1] + 1)) solving for spbrgh1:spbrg1: x = ((f osc /desired baud rate)/64) ? 1 = ((16000000/9600)/64) ? 1 = [25.042] = 25 calculated baud rate = 16000000/(64 (25 + 1)) = 9615 error = (calculated baud rate ? desi red baud rate)/desired baud rate = (9615 ? 9600)/9600 = 0.16%
pic18f6310/6410/8310/8410 ds39635a-page 214 preliminary ? 2004 microchip technology inc. table 17-3: baud rates for asynchronous modes baud rate (k) sync = 0 , brgh = 0 , brg16 = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2 ? ? ? 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 ? ? ? 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 ? ? ? 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 ? ? ? baud rate (k) sync = 0 , brgh = 0 , brg16 = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51 1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12 2.4 2.404 0.16 25 2403 -0.16 12 ? ? ? 9.6 8.929 -6.99 6 ? ? ? ? ? ? 19.2 20.833 8.51 2 ? ? ? ? ? ? 57.6 62.500 8.51 0 ? ? ? ? ? ? 115.2 62.500 -45.75 0 ? ? ? ? ? ? baud rate (k) sync = 0 , brgh = 1 , brg16 = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2???????????? 2.4 ? ? ? ? ? ? 2.441 1.73 255 2403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 ? ? ? baud rate (k) sync = 0 , brgh = 1 , brg16 = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 ? ? ? ? ? ? 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 ? ? ? 19.2 19.231 0.16 12 ? ? ? ? ? ? 57.6 62.500 8.51 3 ? ? ? ? ? ? 115.2 125.000 8.51 1 ? ? ? ? ? ?
? 2004 microchip technology inc. preliminary ds39635a-page 215 pic18f6310/6410/8310/8410 baud rate (k) sync = 0 , brgh = 0 , brg16 = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665 1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415 2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 ? ? ? baud rate (k) sync = 0 , brgh = 0 , brg16 = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 ? ? ? 19.2 19.231 0.16 12 ? ? ? ? ? ? 57.6 62.500 8.51 3 ? ? ? ? ? ? 115.2 125.000 8.51 1 ? ? ? ? ? ? baud rate (k) sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665 1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16 baud rate (k) sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832 1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207 2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103 9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25 19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12 57.6 58.824 2.12 16 55555 3.55 8 ? ? ? 115.2 111.111 -3.55 8 ? ? ? ? ? ? table 17-3: baud rates for asynchronous modes (continued)
pic18f6310/6410/8310/8410 ds39635a-page 216 preliminary ? 2004 microchip technology inc. 17.1.3 auto-baud rate detect the enhanced usart module supports the automatic detection and calibration of baud rate. this feature is active only in asynchronous mode and while the wue bit is clear. the automatic baud rate measurement sequence (figure 17-1) begins whenever a start bit is received and the abden bit is set. the calculation is self-averaging. in the auto-baud rate detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rx1 signal, the rx1 signal is timing the brg. in abd mode, the internal baud rate generator is used as a counter to time the bit period of the incoming serial byte stream. once the abden bit is set, the state machine will clear the brg and look for a start bit. the auto-baud rate detect must receive a byte with the value, 55h (ascii ?u?, which is also the lin bus sync character), in order to calculate the proper bit rate. the measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. after a start bit, the spbrg1 begins counting up, using the preselected clock source on the first rising edge of rx1. after eight bits on the rx1 pin or the fifth rising edge, an accumulated value totalling the proper brg period is left in the spbrgh1:spbrg1 register pair. once the 5th edge is seen (this should correspond to the stop bit), the abden bit is automatically cleared. if a rollover of the brg occurs (an overflow from ffffh to 0000h), the event is trapped by the abdovf status bit (baudcon1<7>). it is set in hardware by brg rollovers and can be set or cleared by the user in software. abd mode remains active after rollover events and the abden bit remains set (figure 17-2). while calibrating the baud rate period, the brg registers are clocked at 1/8th the preconfigured clock rate. note that the brg clock will be configured by the brg16 and brgh bits. independent of the brg16 bit setting, both the spbrg1 and spbrgh1 will be used as a 16-bit counter. this allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the spbrgh1 register. refer to table 17-4 for counter clock rates to the brg. while the abd sequence takes place, the eusart state machine is held in idle. the rc1if interrupt is set once the fifth rising edge on rx1 is detected. the value in the rcreg1 needs to be read to clear the rc1if interrupt. the contents of rcreg1 should be discarded. table 17-4: brg counter clock rates 17.1.3.1 abd and eusart transmission since the brg clock is reversed during abd acquisi- tion, the eusart transmitter cannot be used during abd. this means that whenever the abden bit is set, txreg1 cannot be written to. users should also ensure that abden does not become set during a transmit sequence. failing to do this may result in unpredictable eusart operation. note 1: if the wue bit is set with the abden bit, auto-baud rate detection will occur on the byte following the break character. 2: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusart baud rates are not possible due to bit error rates. overall system timing and communication baud rates must be taken into consideration when using the auto-baud rate detection feature. brg16 brgh brg counter clock 00 f osc /512 01 f osc /128 10 f osc /128 11 f osc /32 note: during the abd sequence, spbrg1 and spbrgh1 are both used as a 16-bit counter, independent of the brg16 setting.
? 2004 microchip technology inc. preliminary ds39635a-page 217 pic18f6310/6410/8310/8410 figure 17-1: automatic baud rate calculation figure 17-2: brg overflow sequence brg value rx1 pin abden bit rc1if bit bit 0 bit 1 (interrupt) read rcreg1 brg clock start auto-cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 stop bit edge #5 001ch note: the abd sequence requires the eusart module to be configured in asynchronous mode and wue = 0 . spbrg1 xxxxh 1ch spbrgh1 xxxxh 00h start bit 0 xxxxh 0000h 0000h ffffh brg clock abden bit rx1 pin abdovf bit brg value
pic18f6310/6410/8310/8410 ds39635a-page 218 preliminary ? 2004 microchip technology inc. 17.2 eusart asynchronous mode the asynchronous mode of operation is selected by clearing the sync bit (txsta1<4>). in this mode, the eusart uses standard non-return-to-zero (nrz) for- mat (one start bit, eight or nine data bits and one stop bit). the most common data format is 8 bits. an on-chip dedi- cated 8-bit/16-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the eusart transmits and receives the lsb first. the eusart?s transmitter and receiver are functionally independent, but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate depending on the brgh and brg16 bits (txsta1<2> and baudcon1<3>). parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. when operating in asynchronous mode, the eusart module consists of the following important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver auto-wake-up on sync break character 12-bit break character transmit auto-baud rate detection 17.2.1 eusart asynchronous transmitter the eusart transmitter block diagram is shown in figure 17-3. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg1. the txreg1 register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg1 register (if available). once the txreg1 register transfers the data to the tsr register (occurs in one t cy ), the txreg1 register is empty and the tx1if flag bit (pir1<4>) is set. this interrupt can be enabled or disabled by setting or clear- ing the interrupt enable bit, tx1ie (pie1<4>). tx1if will be set regardless of the state of tx1ie; it cannot be cleared in software. tx1if is also not cleared immedi- ately upon loading txreg1, but becomes valid in the second instruction cycle following the load instruction. polling tx1if immediately following a load of txreg1 will return invalid results. while tx1if indicates the status of the txreg1 regis- ter, another bit, trmt (txsta1<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr register is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the tsr register is empty. to set up an asynchronous transmission: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit tx1ie. 4. if 9-bit transmission is desired, set transmit bit tx9; can be used as address/data bit. 5. enable the transmission by setting bit txen, which will also set bit tx1if. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg1 register (starts transmission). 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 17-3: eusart transmit block diagram note 1: the tsr register is not mapped in data memory so it is not available to the user. 2: flag bit tx1if is set when enable bit txen is set. tx1if tx1ie interrupt txen baud rate clk spbrg1 baud rate generator tx9d msb lsb data bus txreg1 register tsr register (8) 0 tx9 trmt spen tx1 pin pin buffer and control 8 ? ? ? spbrgh1 brg16
? 2004 microchip technology inc. preliminary ds39635a-page 219 pic18f6310/6410/8310/8410 figure 17-4: asynchronous transmission figure 17-5: asynchronous transmission (back to back) table 17-5: registers associated with asynchronous transmission word 1 word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg1 brg output (shift clock) tx1 (pin) tx1if bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy word 1 stop bit transmit shift reg. write to txreg1 brg output (shift clock) tx1 (pin) tx1if bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy start bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 59 txreg1 eusart transmit register 59 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 59 baudcon1 abdovf rcidl ? sckp brg16 ? wue abden 60 spbrgh1 baud rate generator register high byte 60 spbrg1 baud rate generator register low byte 59 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous transmission.
pic18f6310/6410/8310/8410 ds39635a-page 220 preliminary ? 2004 microchip technology inc. 17.2.2 eusart asynchronous receiver the receiver block diagram is shown in figure 17-6. the data is received on the rx1 pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . this mode would typically be used in rs-232 systems. to set up an asynchronous reception: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit rc1ie. 4. if 9-bit reception is desired, set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rc1if will be set when reception is complete and an interrupt will be generated if enable bit rc1ie was set. 7. read the rcsta1 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg1 register. 9. if any error occurred, clear the error by clearing enable bit cren. 10. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. 17.2.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rc1ip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rc1if bit will be set when reception is complete. the interrupt will be acknowledged if the rc1ie and gie bits are set. 8. read the rcsta1 register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcreg1 to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 17-6: eusart receiv e block diagram x64 baud rate clk baud rate generator rx1 pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg1 register fifo interrupt rc1if rc1ie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? spbrg1 spbrgh1 brg16 or 4
? 2004 microchip technology inc. preliminary ds39635a-page 221 pic18f6310/6410/8310/8410 figure 17-7: asynchronous reception table 17-6: registers associated with asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx1 (pin) rcv buffer reg rcv shift reg read rcv buffer reg rcreg1 rc1if (interrupt flag) oerr bit cren bit word 1 rcreg1 word 2 rcreg1 stop bit note: this timing diagram shows three words appearing on the rx1 input. the rcreg1 (receive buffer) is read after the third word caus ing the oerr (overrun) bit to be set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 59 rcreg1 eusart receive register 59 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 59 baudcon1 abdovf rcidl ? sckp brg16 ? wue abden 60 spbrgh1 baud rate generator register high byte 60 spbrg1 baud rate generator register low byte 59 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception.
pic18f6310/6410/8310/8410 ds39635a-page 222 preliminary ? 2004 microchip technology inc. 17.2.4 auto-wake-up on sync break character during sleep mode, all clocks to the eusart are suspended. because of this, the baud rate generator is inactive and a proper byte reception cannot be per- formed. the auto-wake-up feature allows the controller to wake-up, due to activity on the rx1/dt1 line while the eusart is operating in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit (baudcon<1>). once set, the typical receive sequence on rx1/dt1 is disabled and the eusart remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake-up event consists of a high-to-low transition on the rx1/dt1 line. (this coincides with the start of a sync break or a wake-up signal character for the lin protocol.) following a wake-up event, the module generates an rc1if interrupt. the interrupt is generated synchro- nously to the q clocks in normal operating modes (figure 17-8) and asynchronously, if the device is in sleep mode (figure 17-9). the interrupt condition is cleared by reading the rcreg1 register. the wue bit is automatically cleared once a low-to-high transition is observed on the rx1 line fol- lowing the wake-up event. at this point, the eusart module is in idle mode and returns to normal operation. this signals to the user that the sync break event is over. 17.2.4.1 special considerations using auto-wake-up since auto-wake-up functions by sensing rising edge transitions on rx1/dt1, information with any state changes before the stop bit may signal a false end-of-character and cause data or framing errors. therefore, to work properly, the initial character in the transmission must be all ? 0 ?s. this can be 00h (8 bytes) for standard rs-232 devices, or 000h (12 bits) for lin bus. oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., xt or hs mode). the sync break (or wake-up signal) character must be of suffi- cient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the eusart. 17.2.4.2 special considerations using the wue bit the timing of wue and rc1if events may cause some confusion when it comes to determining the validity of received data. as noted, setting the wue bit places the eusart in an idle mode. the wake-up event causes a receive interrupt by setting the rc1if bit. the wue bit is cleared after this when a rising edge is seen on rx1/dt1. the interrupt condition is then cleared by reading the rcreg1 register. ordinarily, the data in rcreg1 will be dummy data and should be discarded. the fact that the wue bit has been cleared (or is still set) and the rc1if flag is set should not be used as an indicator of the integrity of the data in rcreg1. users should consider implementing a parallel method in firmware to verify received data integrity. to assure that no actual data is lost, check the rcidl bit to verify that a receive operation is not in process. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode.
? 2004 microchip technology inc. preliminary ds39635a-page 223 pic18f6310/6410/8310/8410 figure 17-8: auto-wake-up bit (wue) timings during normal operation figure 17-9: auto-wake-up bit (wue) timings during sleep q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx1/dt1 line rc1if cleared due to user read of rcreg1 note: the eusart remains in idle while the wue bit is set. bit set by user auto-cleared q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx1/dt1 line rc1if cleared due to user read of rcreg1 sleep command executed note 1: if the wake-up event requires long oscillator warm-up time, the auto-clear of the wue bit can occur while the stposc signal is still active. this sequence should not depend on the presence of q clocks. 2: the eusart remains in idle while the wue bit is set. sleep ends auto-cleared note 1 bit set by user
pic18f6310/6410/8310/8410 ds39635a-page 224 preliminary ? 2004 microchip technology inc. 17.2.5 break character sequence the enhanced usart module has the capability of sending the special break character sequences that are required by the lin bus sta ndard. the break character transmit consists of a start bit, followed by twelve ? 0 ? bits and a stop bit. the frame break character is sent whenever the sendb and txen bits (txsta<3> and txsta<5>) are set while the transmit shift register is loaded with data. note that the value of data written to txreg1 will be ignored and all ? 0 ?s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin specification). note that the data value written to the txreg1 for the break character is ignored. the write simply serves the purpose of initiating the proper sequence. the trmt bit indicates when the transmit operation is active or idle, just as it does during normal transmis- sion. see figure 17-10 for the timing of the break character sequence. 17.2.5.1 break and sync transmit sequence the following sequence will send a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin bus master. 1. configure the eusart for the desired mode. 2. set the txen and sendb bits to set up the break character. 3. load the txreg1 with a dummy character to initiate transmission (the value is ignored). 4. write ?55h? to txreg1 to load the sync character into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware. the sync character now transmits in the preconfigured mode. when the txreg1 becomes empty, as indicated by the tx1if, the next data byte can be written to txreg1. 17.2.6 receiving a break character the enhanced usart module can receive a break character in two ways. the first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. this allows for the stop bit transition to be at the correct sampling location (13 bits for break versus start bit and 8 data bits for typical data). the second method uses the auto-wake-up feature described in section 17.2.4 ?auto-wake-up on sync break character? . by enabling this feature, the eusart will sample the next two transitions on rx1/dt1, cause an rc1if interrupt and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud rate detect feature. for both methods, the user can set the abd bit once the tx1if interrupt is observed. figure 17-10: send break character sequence write to txreg1 brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break tx1if bit (transmit buffer reg. empty flag) tx1 (pin) trmt bit (transmit shift reg. empty flag) sendb (transmit shift reg. empty flag) sendb sampled here auto-cleared dummy write
? 2004 microchip technology inc. preliminary ds39635a-page 225 pic18f6310/6410/8310/8410 17.3 eusart synchronous master mode the synchronous master mode is entered by setting the csrc bit (txsta<7>). in this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta<4>). in addition, enable bit, spen (rcsta1<7>), is set in order to configure the tx1 and rx1 pins to ck1 (clock) and dt1 (data) lines, respectively. the master mode indicates that the processor trans- mits the master clock on the ck1 line. clock polarity is selected with the sckp bit (baudcon<4>); setting sckp sets the idle state on ck1 as high, while clearing the bit sets the idle state as low. this option is provided to support microwire devices with this module. 17.3.1 eusart synchronous master transmission the eusart transmitter block diagram is shown in figure 17-3. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg1. the txreg1 register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg1 (if available). once the txreg1 register transfers the data to the tsr register (occurs in one t cycle ), the txreg1 is empty and the tx1if flag bit (pir1<4>) is set. the interrupt can be enabled or disabled by setting or clear- ing the interrupt enable bit, tx1ie (pie1<4>). tx1if is set regardless of the state of enable bit tx1ie; it cannot be cleared in software. it will reset only when new data is loaded into the txreg1 register. while flag bit tx1if indicates the status of the txreg1 register, another bit, trmt (txsta<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to deter- mine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. to set up a synchronous master transmission: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brg16 bit, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit tx1ie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg1 register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 17-11: synchronous transmission bit 0 bit 1 bit 7 word 1 q1 q2 q3q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx1/dt1 rc6/tx1/ck1 pin write to txreg1 reg tx1if bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrg1 = 0 , continuous transmission of two 8-bit words. pin rc6/tx1/ck1 pin (sckp = 0 ) (sckp = 1 )
pic18f6310/6410/8310/8410 ds39635a-page 226 preliminary ? 2004 microchip technology inc. figure 17-12: synchronous transmis sion (through txen) table 17-7: registers associated with synchronous master transmission rc7/rx1/dt1 pin rc6/tx1/ck1 pin write to txreg1 reg tx1if bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 59 txreg1 eusart transmit register 59 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 59 baudcon1 abdovf rcidl ?sckpbrg16 ? wue abden 60 spbrgh1 baud rate generator register high byte 60 spbrg1 baud rate generator register low byte 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission.
? 2004 microchip technology inc. preliminary ds39635a-page 227 pic18f6310/6410/8310/8410 17.3.2 eusart synchronous master reception once synchronous mode is selected, reception is enabled by setting either the single receive enable bit, sren (rcsta1<5>), or the continuous receive enable bit, cren (rcsta1<4>). data is sampled on the rx1 pin on the falling edge of the clock. if enable bit sren is set, only a single word is received. if enable bit cren is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. to set up a synchronous master reception: 1. initialize the spbrgh1:spbrg1 registers for the appropriate baud rate. set or clear the brg16 bit, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, set enable bit rc1ie. 5. if 9-bit reception is desired, set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt flag bit rc1if will be set when reception is complete and an interrupt will be generated if the enable bit rc1ie was set. 8. read the rcsta1 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg1 register. 10. if any error occurred, clear the error by clearing bit cren. 11. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 17-13: synchronous reception (master mode, sren) table 17-8: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 59 rcreg1 eusart receive register 59 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 59 baudcon1 abdovf rcidl ? sckp brg16 ? wue abden 60 spbrgh1 baud rate generator register high byte 60 spbrg1 baud rate generator register low byte 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master reception. cren bit rc7/rx1/dt1 rc6/tx1/ck1 pin write to sren bit sren bit rc1if bit (interrupt) read rcreg1 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? q1 q2 q3 q4 note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . rc6/tx1/ck1 pin pin (sckp = 0 ) (sckp = 1 )
pic18f6310/6410/8310/8410 ds39635a-page 228 preliminary ? 2004 microchip technology inc. 17.4 eusart synchronous slave mode synchronous slave mode is entered by clearing bit csrc (txsta<7>). this mode differs from the synchronous master mode in that the shift clock is supplied externally at the ck1 pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in any low-power mode. 17.4.1 eusart synchronous slave transmit the operation of the synchronous master and slave modes are identical except in the case of the sleep mode. if two words are written to the txreg1 and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg1 register. c) flag bit tx1if will not be set. d) when the first word has been shifted out of tsr, the txreg1 register will transfer the second word to the tsr and flag bit tx1if will now be set. e) if enable bit tx1ie is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave transmission: 1. enable the synchronous slave serial port by setting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, set enable bit tx1ie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg1x register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 17-9: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 59 txreg1 eusart transmit register 59 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 59 baudcon1 abdovf rcidl ? sckp brg16 ? wue abden 60 spbrgh1 baud rate generator register high byte 60 spbrg1 baud rate generator register low byte 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave transmission.
? 2004 microchip technology inc. preliminary ds39635a-page 229 pic18f6310/6410/8310/8410 17.4.2 eusart synchronous slave reception the operation of the synchronous master and slave modes is identical except in the case of sleep or any idle mode and bit sren, which is a ?don?t care? in slave mode. if receive is enabled by setting the cren bit prior to entering sleep or any idle mode, then a word may be received while in this low-power mode. once the word is received, the rsr register will transfer the data to the rcreg1 register; if the rc1ie enable bit is set, the interrupt generated will wake the chip from the low-power mode. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rc1ie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rc1if will be set when reception is complete. an interrupt will be generated if enable bit rc1ie was set. 6. read the rcsta1 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg1 register. 8. if any error occurred, clear the error by clearing bit cren. 9. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 17-10: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 59 rcreg1 eusart receive register 59 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 59 baudcon1 abdovf rcidl ?sckpbrg16 ? wue abden 60 spbrgh1 baud rate generator register high byte 60 spbrg1 baud rate generator register low byte 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception.
pic18f6310/6410/8310/8410 ds39635a-page 230 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 231 pic18f6310/6410/8310/8410 18.0 addressable universal synchronous asynchronous receiver transmitter (ausart) the addressable universal synchronous asynchro- nous receiver transmitter (ausart) module is very similar in function to the enhanced usart module, discussed in the previous chapter. it is provided as an additional channel for serial communication with external devices, for those situations that do not require auto-baud detection or lin bus support. the ausart can be configured in the following modes: asynchronous (full-duplex) synchronous ? master (half-duplex) synchronous ? slave (half-duplex) the pins of the ausart module are multiplexed with the functions of portg (rg1/tx2/ck2 and rg2/rx2/dt2, respectively). in order to configure these pins as an ausart: bit spen (rcsta2<7>) must be set (= 1 ) bit trisg<2> must be set (= 1 ) bit trisg<1> must be cleared (= 0 ) for asynchro- nous and synchronous master modes bit trisg<1> must be set (= 1 ) for synchronous slave mode the operation of the addressable usart module is controlled through two registers, txsta2 and rxsta2. these are detailed in register 18-1 and register 18-2 respectively. note: the usart control will automatically reconfigure the pin from input to output as needed.
pic18f6310/6410/8310/8410 ds39635a-page 232 preliminary ? 2004 microchip technology inc. register 18-1: txsta2: ausart transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen (1) sync ?brghtrmttx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode: don?t care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled note 1: sren/cren overrides txen in sync mode. bit 4 sync: ausart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as ? 0 ? bit 2 brgh: high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data can be address/data bit or a parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds39635a-page 233 pic18f6310/6410/8310/8410 register 18-2: rcsta2: ausart receive status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : don?t care. synchronous mode ? master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave: don?t care. bit 4 cren: continuous receive enable bit asynchronous mode: 1 = enables receiver 0 = disables receiver synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection, enables interrupt and loads the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 9-bit (rx9 = 0 ) : don?t care. bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcreg register and receiving next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 234 preliminary ? 2004 microchip technology inc. 18.1 ausart baud rate generator (brg) the brg is a dedicated 8-bit generator that supports both the asynchronous and synchronous modes of the ausart. the spbrg2 register controls the period of a free running timer. in asynchronous mode, bit brgh (txsta<2>) also controls the baud rate. in synchro- nous mode, brgh is ignored. table 18-1 shows the formula for computation of the baud rate for different ausart modes, which only apply in master mode (internally generated clock). given the desired baud rate and f osc , the nearest integer value for the spbrg2 register can be calcu- lated using the formulas in table 18-1. from this, the error in baud rate can be determined. an example calculation is shown in example 18-1. typical baud rates and error values for the various asynchronous modes are shown in table 18-2. it may be advanta- geous to use the high baud rate (brgh = 1 ) to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. writing a new value to the spbrg2 register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 18.1.1 operation in power managed modes the device clock is used to generate the desired baud rate. when one of the power managed modes is entered, the new clock source may be operating at a different frequency. this may require an adjustment to the value in the spbrg2 register. 18.1.2 sampling the data on the rx2 pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx2 pin. table 18-1: baud rate formulas example 18-1: calculating baud rate error table 18-2: registers associated with the baud rate generator configuration bits brg/ausart mode baud rate formula sync brgh 00 asynchronous f osc /[64 (n + 1)] 01 asynchronous f osc /[16 (n + 1)] 1x synchronous f osc /[4 (n + 1)] legend: x = don?t care, n = value of spbrg2 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page txsta2 csrc tx9 txen sync ?brgh trmt tx9d 60 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 60 spbrg2 baud rate generator register 60 legend: shaded cells are not used by the brg. for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, brgh = 0: desired baud rate = f osc /(64 ([spbrg2] + 1)) solving for spbrg2: x = ((f osc /desired baud rate)/64) ? 1 = ((16000000/9600)/64) ? 1 = [25.042] = 25 calculated baud rate = 16000000/(64 (25 + 1)) = 9615 error = (calculated baud rate ? desi red baud rate)/desired baud rate = (9615 ? 9600)/9600 = 0.16%
? 2004 microchip technology inc. preliminary ds39635a-page 235 pic18f6310/6410/8310/8410 table 18-3: baud rates for asynchronous modes brgh = 0 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz baud rate (k) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2 ? ? ? 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 ? ? ? 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 ? ? ? 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 ? ? ? brgh = 0 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz baud rate (k) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51 1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12 2.4 2.404 0.16 25 2403 -0.16 12 ? ? ? 9.6 8.929 -6.99 6 ? ? ? ? ? ? 19.2 20.833 8.51 2 ? ? ? ? ? ? 57.6 62.500 8.51 0 ? ? ? ? ? ? 115.2 62.500 -45.75 0 ? ? ? ? ? ? baud rate (k) brgh = 1 f osc = 40.000 mhz f osc = 20.000 mhz f osc = 10.000 mhz f osc = 8.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2???????????? 2.4 ? ? ? ? ? ? 2.441 1.73 255 2403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 ? ? ? baud rate (k) brgh = 1 f osc = 4.000 mhz f osc = 2.000 mhz f osc = 1.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 ? ? ? ? ? ? 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 ? ? ? 19.2 19.231 0.16 12 ? ? ? ? ? ? 57.6 62.500 8.51 3 ? ? ? ? ? ? 115.2 125.000 8.51 1 ? ? ? ? ? ?
pic18f6310/6410/8310/8410 ds39635a-page 236 preliminary ? 2004 microchip technology inc. 18.2 ausart asynchronous mode the asynchronous mode of operation is selected by clearing the sync bit (txsta2<4>). in this mode, the ausart uses standard non-return-to-zero (nrz) for- mat (one start bit, eight or nine data bits and one stop bit). the most common data format is 8 bits. an on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the ausart transmits and receives the lsb first. the ausart?s transmitter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the brgh bit (txsta2<2>). parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. when operating in asynchronous mode, the ausart module consists of the following important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 18.2.1 ausart asynchronous transmitter the ausart transmitter block diagram is shown in figure 18-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg2. the txreg2 register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg2 register (if available). once the txreg2 register transfers the data to the tsr register (occurs in one t cy ), the txreg2 register is empty and the tx2if flag bit (pir3<4>) is set. this interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, tx2ie (pie3<4>). tx2if will be set regardless of the state of tx2ie; it cannot be cleared in software. tx2if is also not cleared immediately upon loading txreg2, but becomes valid in the second instruction cycle following the load instruction. polling tx2if immediately following a load of txreg2 will return invalid results. while tx2if indicates the status of the txreg2 regis- ter, another bit, trmt (txsta2<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr register is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the tsr register is empty. to set up an asynchronous transmission: 1. initialize the spbrg2 register for the appropriate baud rate. set or clear the brgh bit, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit tx2ie. 4. if 9-bit transmission is desired, set transmit bit tx9. can be used as address/data bit. 5. enable the transmission by setting bit txen, which will also set bit tx2if. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg2 register (starts transmission). 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 18-1: ausart transmit block diagram note 1: the tsr register is not mapped in data memory so it is not available to the user. 2: flag bit tx2if is set when enable bit txen is set. tx2if tx2ie interrupt txen baud rate clk spbrg2 baud rate generator tx9d msb lsb data bus txreg2 register tsr register (8) 0 tx9 trmt spen tx2 pin pin buffer and control 8 ? ? ?
? 2004 microchip technology inc. preliminary ds39635a-page 237 pic18f6310/6410/8310/8410 figure 18-2: asynchronous transmission figure 18-3: asynchronous transmission (back to back) table 18-4: registers associated with asynchronous transmission word 1 word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg2 brg output (shift clock) tx2 (pin) tx2if bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy word 1 stop bit transmit shift reg. write to txreg2 brg output (shift clock) tx2 (pin) tx2if bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy start bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir3 ? ? rc2if tx2if ? ? ? ccp3if 59 pie3 ? ? rc2ie tx2ie ? ? ? ccp3ie 59 ipr3 ? ? rc2ip tx2ip ? ? ? ccp3ip 59 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 60 txreg2 ausart transmit register 60 txsta2 csrc tx9 txen sync ? brgh trmt tx9d 60 spbrg2 baud rate generator register 60 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous transmission.
pic18f6310/6410/8310/8410 ds39635a-page 238 preliminary ? 2004 microchip technology inc. 18.2.2 ausart asynchronous receiver the receiver block diagram is shown in figure 18-4. the data is received on the rx2 pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . this mode would typically be used in rs-232 systems. to set up an asynchronous reception: 1. initialize the spbrg2 register for the appropriate baud rate. set or clear the brgh bit, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit rc2ie. 4. if 9-bit reception is desired, set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rc2if will be set when reception is complete and an interrupt will be generated if enable bit rc2ie was set. 7. read the rcsta2 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg2 register. 9. if any error occurred, clear the error by clearing enable bit cren. 10. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. 18.2.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrg2 register for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rc2ip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rc2if bit will be set when reception is complete. the interrupt will be acknowledged if the rc2ie and gie bits are set. 8. read the rcsta2 register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcreg2 to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 18-4: ausart recei ve block diagram x64 baud rate clk baud rate generator rx2 pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg2 register fifo interrupt rc2if rc2ie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? spbrg2 or 4
? 2004 microchip technology inc. preliminary ds39635a-page 239 pic18f6310/6410/8310/8410 figure 18-5: asynchronous reception table 18-5: registers associated with asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx2 (pin) rcv buffer reg rcv shift reg read rcv buffer reg rcreg2 rc2if (interrupt flag) oerr bit cren word 1 rcreg2 word 2 rcreg2 stop bit note: this timing diagram shows three words appearing on the rx2 input. the rcreg2 (receive buffer) is read after the third word causing the oerr (overrun) bit to be set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir3 ? ? rc2if tx2if ? ? ? ccp3if 59 pie3 ? ? rc2ie tx2ie ? ? ? ccp3ie 59 ipr3 ? ? rc2ip tx2ip ? ? ? ccp3ip 59 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 60 rcreg2 ausart receive register 60 txsta2 csrc tx9 txen sync ?brgh trmt tx9d 60 spbrg2 baud rate generator register 60 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception.
pic18f6310/6410/8310/8410 ds39635a-page 240 preliminary ? 2004 microchip technology inc. 18.3 ausart synchronous master mode the synchronous master mode is entered by setting the csrc bit (txsta2<7>). in this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txsta2<4>). in addition, enable bit spen (rcsta2<7>) is set in order to configure the tx2 and rx2 pins to ck2 (clock) and dt2 (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck2 line. 18.3.1 ausart synchronous master transmission the ausart transmitter block diagram is shown in figure 18-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg2. the txreg2 register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg2 (if available). once the txreg2 register transfers the data to the tsr register (occurs in one t cycle ), the txreg2 is empty and the tx2if flag bit (pir3<4>) is set. the interrupt can be enabled or disabled by setting or clear- ing the interrupt enable bit tx2ie (pie3<4>). tx2if is set regardless of the state of enable bit tx2ie; it cannot be cleared in software. it will reset only when new data is loaded into the txreg2 register. while flag bit tx2if indicates the status of the txreg2 register, another bit, trmt (txsta2<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to deter- mine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. to set up a synchronous master transmission: 1. initialize the spbrg2 register for the appropriate baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit tx2ie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg2 register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 18-6: synchronous transmission bit 0 bit 1 bit 7 word 1 q1 q2 q3q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rx2/dt2 pin tx2/ck2 pin write to txreg2 reg tx2if bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrg2 = 0 , continuous transmission of two 8-bit words.
? 2004 microchip technology inc. preliminary ds39635a-page 241 pic18f6310/6410/8310/8410 figure 18-7: synchronous transmissi on (through txen) table 18-6: registers associated with synchronous master transmission rx2/dt2 pin tx2/ck2 pin write to txreg2 reg tx2if bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir3 ? ? rc2if tx2if ? ? ? ccp3if 59 pie3 ? ? rc2ie tx2ie ? ? ? ccp3ie 59 ipr3 ? ? rc2ip tx2ip ? ? ? ccp3ip 59 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 60 txreg2 ausart transmit register 60 txsta2 csrc tx9 txen sync ? brgh trmt tx9d 60 spbrg2 baud rate generator register 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission.
pic18f6310/6410/8310/8410 ds39635a-page 242 preliminary ? 2004 microchip technology inc. 18.3.2 ausart synchronous master reception once synchronous mode is selected, reception is enabled by setting either the single receive enable bit, sren (rcsta2<5>), or the continuous receive enable bit, cren (rcsta2<4>). data is sampled on the rx2 pin on the falling edge of the clock. if enable bit sren is set, only a single word is received. if enable bit cren is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. to set up a synchronous master reception: 1. initialize the spbrg2 register for the appropriate baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, set enable bit rc2ie. 5. if 9-bit reception is desired, set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt flag bit, rc2if, will be set when reception is complete and an interrupt will be generated if the enable bit rc2ie was set. 8. read the rcsta2 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg2 register. 10. if any error occurred, clear the error by clearing bit cren. 11. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 18-8: synchronous reception (master mode, sren) table 18-7: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir3 ? ? rc2if tx2if ? ? ? ccp3if 59 pie3 ? ? rc2ie tx2ie ? ? ? ccp3ie 59 ipr3 ? ? rc2ip tx2ip ? ? ? ccp3ip 59 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 60 rcreg2 ausart receive register 60 txsta2 csrc tx9 txen sync ? brgh trmt tx9d 60 spbrg2 baud rate generator register low byte 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master reception. cren bit rx2/dt2 pin tx2/ck2 pin write to bit sren sren bit rc2if bit (interrupt) read rcreg2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? q1 q2 q3 q4 note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 .
? 2004 microchip technology inc. preliminary ds39635a-page 243 pic18f6310/6410/8310/8410 18.4 ausart synchronous slave mode synchronous slave mode is entered by clearing bit csrc (txsta2<7>). this mode differs from the synchronous master mode in that the shift clock is supplied externally at the ck2 pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in any low-power mode. 18.4.1 ausart synchronous slave transmit the operation of the synchronous master and slave modes are identical except in the case of the sleep mode. if two words are written to the txreg2 and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg2 register. c) flag bit tx2if will not be set. d) when the first word has been shifted out of tsr, the txreg2 register will transfer the second word to the tsr and flag bit tx2if will now be set. e) if enable bit tx2ie is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave transmission: 1. enable the synchronous slave serial port by setting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, set enable bit tx2ie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg2 register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 18-8: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir3 ? ? rc2if tx2if ? ? ? ccp3if 59 pie3 ? ? rc2ie tx2ie ? ? ? ccp3ie 59 ipr3 ? ? rc2ip tx2ip ? ? ? ccp3ip 59 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 60 txreg2 ausart transmit register 60 txsta2 csrc tx9 txen sync ? brgh trmt tx9d 60 spbrg2 baud rate generator register low byte 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave transmission.
pic18f6310/6410/8310/8410 ds39635a-page 244 preliminary ? 2004 microchip technology inc. 18.4.2 ausart synchronous slave reception the operation of the synchronous master and slave modes is identical except in the case of sleep, or any idle mode and bit sren, which is a ?don?t care? in slave mode. if receive is enabled by setting the cren bit prior to entering sleep, or any idle mode, then a word may be received while in this low-power mode. once the word is received, the rsr register will transfer the data to the rcreg2 register; if the rc2ie enable bit is set, the interrupt generated will wake the chip from low-power mode. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rc2ie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rc2if will be set when reception is complete. an interrupt will be generated if enable bit rc2ie was set. 6. read the rcsta2 register to get the 9th bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg2 register. 8. if any error occurred, clear the error by clearing bit cren. 9. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 18-9: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir3 ? ?rc2if tx2if ? ? ? ccp3if 59 pie3 ? ? rc2ie tx2ie ? ? ? ccp3ie 59 ipr3 ? ? rc2ip tx2ip ? ? ? ccp3ip 59 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 60 rcreg2 ausart receive register 60 txsta2 csrc tx9 txen sync ? brgh trmt tx9d 60 spbrg2 baud rate generator register low byte 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception.
? 2004 microchip technology inc. preliminary ds39635a-page 245 pic18f6310/6410/8310/8410 19.0 10-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has 12 inputs for the pic18fx310/x410 devices. this module allows conversion of an analog input signal to a corresponding 10-bit digital number. the module has five registers: a/d result high register (adresh) a/d result low register (adresl) a/d control register 0 (adcon0) a/d control register 1 (adcon1) a/d control register 2 (adcon2) the adcon0 register, shown in register 19-1, controls the operation of the a/d module. the adcon1 register, shown in register 19-2, configures the functions of the port pins. the adcon2 register, shown in register 19-3, configures the a/d clock source, programmed acquisition time and justification. register 19-1: adcon0 register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-2 chs3:chs0: analog channel select bits 0000 = channel 0 (an0) 0001 = channel 1 (an1) 0010 = channel 2 (an2) 0011 = channel 3 (an3) 0100 = channel 4 (an4) 0101 = channel 5 (an5) 0110 = channel 6 (an6) 0111 = channel 7 (an7) 1000 = channel 8 (an8) 1001 = channel 9 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 1100 = unimplemented (1) 1101 = unimplemented (1) 1110 = unimplemented (1) 1111 = unimplemented (1) note 1: performing a conversion on unimplemented channels will return a floating input measurement. bit 1 go/done : a/d conversion status bit when adon = 1 : 1 = a/d conversion in progress 0 = a/d idle bit 0 adon: a/d on bit 1 = a/d converter module is enabled 0 = a/d converter module is disabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 246 preliminary ? 2004 microchip technology inc. register 19-2: adcon1 register u-0 u-0 r/w-0 r/w-0 r/w-q r/w-q r/w-q r/w-q ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 vcfg1: voltage reference configuration bit (v ref - source): 1 = v ref - (an2) 0 = av ss bit 4 vcfg0: voltage reference configuration bit (v ref + source): 1 = v ref + (an3) 0 = av dd bit 3-0 pcfg3:pcfg0: a/d port configuration control bits: legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown a = analog input d = digital i/o pcfg3: pcfg0 an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 0000 a aaaaaaaaaaa 0001 a aaaaaaaaaaa 0010 a aaaaaaaaaaa 0011 a aaaaaaaaaaa 0100 d aaaaaaaaaaa 0101 d daaaaaaaaaa 0110 d ddaaaaaaaaa 0111 d dddaaaaaaaa 1000 d ddddaaaaaaa 1001 d dddddaaaaaa 1010 d ddddddaaaaa 1011 d dddddddaaaa 1100 d ddddddddaaa 1101 d dddddddddaa 1110 d dddddddddda 1111 d ddddddddddd
? 2004 microchip technology inc. preliminary ds39635a-page 247 pic18f6310/6410/8310/8410 register 19-3: adcon2 register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 bit 7 bit 0 bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6 unimplemented: read as ? 0 ? bit 5-3 acqt2:acqt0: a/d acquisition time select bits 111 = 20 t ad 110 = 16 t ad 101 = 12 t ad 100 = 8 t ad 011 = 6 t ad 010 = 4 t ad 001 = 2 t ad 000 = 0 t ad (1) bit 2-0 adcs2:adcs0: a/d conversion clock select bits 111 = f rc (clock derived from a/d rc oscillator) (1) 110 = f osc /64 101 = f osc /16 100 = f osc /4 011 = f rc (clock derived from a/d rc oscillator) (1) 010 = f osc /32 001 = f osc /8 000 = f osc /2 note 1: if the a/d f rc clock source is selected, a delay of one t cy (instruction cycle) is added before the a/d clock starts. this allows the sleep instruction to be executed before starting a conversion. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 248 preliminary ? 2004 microchip technology inc. the analog reference voltage is software selectable to either the device?s positive and negative supply voltage (av dd and av ss ), or the voltage level on the ra3/an3/v ref + and ra2/an2/v ref - pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion in progress is aborted. each port pin associated with the a/d converter can be configured as an analog input or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is com- plete, the result is loaded into the adresh/adresl registers, the go/done bit (adcon0 register) is cleared and the a/d interrupt flag bit, adif, is set. the block diagram of the a/d module is shown in figure 19-1. figure 19-1: a/d block diagram (input voltage) v ain v ref + reference voltage av dd vcfg1:vcfg0 chs3:chs0 an7 an6 an5 an4 an3 an2 an1 an0 0111 0110 0101 0100 0011 0010 0001 0000 10-bit converter v ref - av ss a/d an11 an10 an9 an8 1011 1010 1001 1000 note 1: i/o pins have diode protection to v dd and v ss . 0 x 1 x x 1 x 0
? 2004 microchip technology inc. preliminary ds39635a-page 249 pic18f6310/6410/8310/8410 the value in the adresh:adresl registers is not modified for a power-on reset. the adresh:adresl registers will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 19.1 ?a/d acquisition requirements? . after this acquisi- tion time has elapsed, the a/d conversion can be started. an acquisition time can be programmed to occur between setting the go/done bit and the actual start of the conversion. the following steps should be followed to perform an a/d conversion: 1. configure the a/d module: configure analog pins, voltage reference and digital i/o (adcon1) select a/d input channel (adcon0) select a/d acquisition time (adcon2) select a/d conversion clock (adcon2) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set gie bit 3. wait the required acquisition time (if required). 4. start conversion: set go/done bit (adcon0 register) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear bit adif, if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 3 t ad is required before the next acquisition starts. figure 19-2: a/d transfer function figure 19-3: analog input model digital code output 3feh 003h 002h 001h 000h 0.5 lsb 1 lsb 1.5 lsb 2 lsb 2.5 lsb 1022 lsb 1022.5 lsb 3 lsb analog input voltage 3ffh 1023 lsb 1023.5 lsb v ain c pin rs anx 5 pf v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 25 pf v ss v dd 100 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions = sampling switch resistance r ss v dd 6v sampling switch 5v 4v 3v 2v 123 4 (k ? )
pic18f6310/6410/8310/8410 ds39635a-page 250 preliminary ? 2004 microchip technology inc. 19.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 19-3. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k ? . after the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. to calculate the minimum acquisition time, equation 19-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. example 19-3 shows the calculation of the minimum required acquisition time t acq . this calculation is based on the following application system assumptions: c hold = 25 pf rs = 2.5 k ? conversion error 1/2 lsb v dd =5v rss = 2 k ? temperature = 85 c (system max.) equation 19-1: acquisition time equation 19-2: a/d minimum charging time equation 19-3: calculating the minimum required acquisition time note: when the conversion is started, the holding capacitor is disconnected from the input pin. t acq = amplifier settling time + holding capacitor charging time + temperature coefficient =t amp + t c + t coff v hold = (v ref ? (v ref /2048)) (1 ? e (-t c /c hold (r ic + r ss + r s )) ) or t c = -(c hold )(r ic + r ss + r s ) ln(1/2048) t acq =t amp + t c + t coff t amp =0.2 s t coff = (temp ? 25 c)(0.02 s/ c) (50 c ? 25 c)(0.02 s/ c) 1.2 s temperature coefficient is only required for temperatures > 25 c. below 25 c, t coff = 0 ms. t c = -(c hold )(r ic + r ss + r s ) ln(1/2047) s -(25 pf) (1 k ? + 2 k ? + 2.5 k ? ) ln(0.0004883) s 5.03 s t acq =0.2 s + 5 s + 1.2 s 6.4 s
? 2004 microchip technology inc. preliminary ds39635a-page 251 pic18f6310/6410/8310/8410 19.2 selecting and configuring automatic acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensur- ing the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this occurs when the acqt2:acqt0 bits (adcon2<5:3>) remain in their reset state (? 000 ?) and is compatible with devices that do not offer programmable acquisition times. if desired, the acqt bits can be set to select a programmable acquisition time for the a/d module. when the go/done bit is set, the a/d module contin- ues to sample the input for the selected acquisition time, then automatically begins a conversion. since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the go/done bit. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/d begins sampling the currently selected channel again. if an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended, or if the conversion has begun. 19.3 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 11 t ad per 10-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : 2 t osc 4 t osc 8 t osc 16 t osc 32 t osc 64 t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be as short as possible, but greater than the minimum t ad (approximately 2 s, see parameter 130 for more information). table 19-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 19-1: t ad vs. device operating frequencies ad clock source (t ad ) maximum device frequency operation adcs2:adcs0 pic18f6x10/8x10 pic18lf6x10/8x10 (4) 2 t osc 000 1.25 mhz 666 khz 4 t osc 100 2.50 mhz 1.33 mhz 8 t osc 001 5.00 mhz 2.66 mhz 16 t osc 101 10.0 mhz 5.33 mhz 32 t osc 010 20.0 mhz 10.65 mhz 64 t osc 110 40.0 mhz 21.33 mhz rc (3) x11 1.00 mhz (1) 1.00 mhz (2) note 1: the rc source has a typical t ad time of 4 s. 2: the rc source has a typical t ad time of 6 s. 3: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion or the a/d accuracy may be out of specification. 4: low-power (pic18lfxxxx) devices only.
pic18f6310/6410/8310/8410 ds39635a-page 252 preliminary ? 2004 microchip technology inc. 19.4 operation in power managed modes the selection of the automatic acquisition time and a/d conversion clock is determined in part by the clock source and frequency while in a power managed mode. if the a/d is expected to operate while the device is in a power managed mode, the acqt2:acqt0 and adcs2:adcs0 bits in adcon2 should be updated in accordance with the power managed mode clock that will be used. after the power managed mode is entered, an a/d acquisition or conversion may be started. once an acquisition or conversion is started, the device should continue to be clocked by the same power managed mode clock source until the conver- sion has been completed. if desired, the device may be placed into the corresponding power managed idle mode during the conversion. if the power managed mode clock frequency is less than 1 mhz, the a/d rc clock source should be selected. operation in the sleep mode requires the a/d f rc clock to be selected. if bits acqt2:acqt0 are set to ? 000 ? and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the sleep instruction and entry to sleep mode. the idlen and scs bits in the osccon register must have already been cleared prior to starting the conversion. 19.5 configuring analog port pins the adcon1, trisa and trisf registers all configure the a/d port pins. the port pins needed as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs3:chs0 bits and the tris bits. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an analog input. analog levels on a digitally configured input will be accurately converted. 2: analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device?s specification limits.
? 2004 microchip technology inc. preliminary ds39635a-page 253 pic18f6310/6410/8310/8410 19.6 a/d conversions figure 19-4 shows the operation of the a/d converter after the go bit has been set and the acqt2:acqt0 bits are cleared. a conversion is started after the follow- ing instruction to allow entry into sleep mode before the conversion begins. figure 19-5 shows the operation of the a/d converter after the go bit has been set and the acqt2:acqt0 bits are set to ? 010 ? and selecting a 4 t ad acquisition time before the conversion starts. clearing the go/done bit during a conversion will abort the current conversion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. this means the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is completed or aborted, a 2t ad wait is required before the next acquisition can be started. after this wait, acquisition on the selected channel is automatically started. 19.7 discharge the discharge phase is used to initialize the value of the capacitor array. the array is discharged before every sample. this feature helps to optimize the unity-gain amplifier as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous measure values. figure 19-4: a/d conversion t ad cycles (acqt<2:0> = 000 , t acq = 0 ) figure 19-5: a/d conversion t ad cycles (acqt<2:0> = 010 , t acq = 4 t ad ) note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 on the following cycle: t ad 1 discharge 1 2 3 4 5 6 7 8 11 set go bit (holding capacitor is disconnected) 9 10 conversion starts 1 2 3 4 (holding capacitor continues acquiring input) t acqt cycles t ad cycles automatic acquisition time b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. on the following cycle: t ad 1 discharge
pic18f6310/6410/8310/8410 ds39635a-page 254 preliminary ? 2004 microchip technology inc. 19.8 use of the ccp2 trigger an a/d conversion can be started by the ?special event trigger? of the ccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be pro- grammed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d acquisition and conversion and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to auto- matically repeat the a/d acquisition period with minimal software overhead (moving adresh/adresl to the desired location). the appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate t acq time selected before the ?special event trigger? sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the ?special event trigger? will be ignored by the a/d module, but will still reset the timer1 (or timer3) counter. table 19-2: registers associated with a/d operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir1 pspif adif rc1if tx1if sspif ccp1if tmr2if tmr1if 59 pie1 pspie adie rc1ie tx1ie sspie ccp1ie tmr2ie tmr1ie 59 ipr1 pspip adip rc1ip tx1ip sspip ccp1ip tmr2ip tmr1ip 59 pir2 oscfif cmif ? ? bclif hlvdif tmr3if ccp2if 59 pie2 oscfie cmie ? ? bclie hlvdie tmr3ie ccp2ie 59 ipr2 oscfip cmip ? ? bclip hlvdip tmr3ip ccp2ip 59 adresh a/d result register high byte 58 adresl a/d result register low byte 58 adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon 58 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 58 adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 58 porta ra7 (1) ra6 (1) ra5 ra4 ra3 ra2 ra1 ra0 60 trisa trisa7 (1) trisa6 (1) porta data direction register 60 portf read portf pins, write latf latch 60 trisf portf data direction register 60 latf portf output data latch 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for a/d conversion. note 1: these pins may be configured as port pins depending on the oscillator mode selected.
? 2004 microchip technology inc. preliminary ds39635a-page 255 pic18f6310/6410/8310/8410 20.0 comparator module the analog comparator module contains two comparators that can be configured in a variety of ways. the inputs can be selected from the analog inputs multiplexed with pins rf3 through rf6, as well as the on-chip voltage reference (see section 21.0 ?comparator voltage reference module? ). the digi- tal outputs (normal or inverted) are available at the pin level and can also be read through the control register. the cmcon register (register 20-1) selects the comparator input and output configuration. block diagrams of the various comparator configurations are shown in figure 20-1. register 20-1: cmcon register r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 c2out c1out c2inv c1inv cis cm2 cm1 cm0 bit 7 bit 0 bit 7 c2out : comparator 2 output bit when c2inv = 0 : 1 = c2 v in + > c2 v in - 0 = c2 v in + < c2 v in - when c2inv = 1 : 1 = c2 v in + < c2 v in - 0 = c2 v in + > c2 v in - bit 6 c1out : comparator 1 output bit when c1inv = 0 : 1 = c1 v in + > c1 v in - 0 = c1 v in + < c1 v in - when c1inv = 1 : 1 = c1 v in + < c1 v in - 0 = c1 v in + > c1 v in - bit 5 c2inv : comparator 2 output inversion bit 1 = c2 output inverted 0 = c2 output not inverted bit 4 c1inv : comparator 1 output inversion bit 1 = c1 output inverted 0 = c1 output not inverted bit 3 cis : comparator input switch bit when cm2:cm0 = 110 : 1 =c1 v in - connects to rf5/an10 c2 v in - connects to rf3/an8 0 =c1 v in - connects to rf6/an11 c2 v in - connects to rf4/an9 bit 2-0 cm2:cm0 : comparator mode bits figure 20-1 shows the comparator modes and the cm2:cm0 bit settings. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 256 preliminary ? 2004 microchip technology inc. 20.1 comparator configuration there are eight modes of operation for the compara- tors, shown in figure 20-1. bits cm2:cm0 of the cmcon register are used to select these modes. the trisf register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in section 26.0 ?electrical characteristics? . figure 20-1: comparator i/o operating modes note: comparator interrupts should be disabled during a comparator mode change; otherwise, a false interrupt may occur. c1 rf6/an11 v in - v in + rf5/an10/ off (read as ? 0 ?) comparators reset (por default value) a a cm2:cm0 = 000 c2 rf4/an9 v in - v in + rf3/an8 off (read as ? 0 ?) a a c1 v in - v in + c1out two independent comparators a a cm2:cm0 = 010 c2 v in - v in + c2out a a c1 v in - v in + c1out two common reference comparators a a cm2:cm0 = 100 c2 v in - v in + c2out a d c2 v in - v in + off (read as ? 0 ?) one independent comparator with output d d cm2:cm0 = 001 c1 v in - v in + c1out a a c1 v in - v in + off (read as ? 0 ?) comparators off d d cm2:cm0 = 111 c2 v in - v in + off (read as ? 0 ?) d d c1 v in - v in + c1out four inputs multiplexed to two comparators a a cm2:cm0 = 110 c2 v in - v in + c2out a a from v ref module cis = 0 cis = 1 cis = 0 cis = 1 c1 v in - v in + c1out two common reference comparators with outputs a a cm2:cm0 = 101 c2 v in - v in + c2out a d a = analog input, port reads zeros always d = digital input cis (cmcon<3>) is the comparator input switch cv ref c1 v in - v in + c1out two independent comparators with outputs a a cm2:cm0 = 011 c2 v in - v in + c2out a a rf1/an6/c2out* rf2/an7/c1out* cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ cv ref rf4/an9 rf3/an8 rf2/an7/c1out* rf1/an6/c2out* rf6/an11 rf5/an10/ cv ref rf4/an9 rf3/an8 rf2/an7/c1out* * setting the trisf<2:1> bits will disable the comparator outputs by configuring the pins as inputs.
? 2004 microchip technology inc. preliminary ds39635a-page 257 pic18f6310/6410/8310/8410 20.2 comparator operation a single comparator is shown in figure 20-2, along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 20-2 represent the uncertainty, due to input offsets and response time. 20.3 comparator reference depending on the comparator operating mode, either an external or internal voltage reference may be used. the analog signal present at v in - is compared to the signal at v in + and the digital output of the comparator is adjusted accordingly (figure 20-2). figure 20-2: single comparator 20.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the com- parators operate from the same, or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd and can be applied to either pin of the comparator(s). 20.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference from the com- parator voltage reference module. this module is described in more detail in section 21.0 ?comparator voltage reference module? . the internal reference is only available in the mode where four inputs are multiplexed to two comparators (cm2:cm0 = 110 ). in this mode, the internal voltage reference is applied to the v in + pin of both comparators. 20.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. if the internal ref- erence is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. otherwise, the maximum delay of the comparators should be used (see section 26.0 ?electrical characteristics? ). 20.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read-only. the comparator outputs may also be directly output to the rf2 and rf1 i/o pins. when enabled, multiplexors in the output path of the rf2 and rf1 pins will switch and the output of each pin will be the unsynchronized output of the comparator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 20-3 shows the comparator output block diagram. the trisf bits will still function as an output enable/ disable for the rf2 and rf1 pins while in this mode. the polarity of the comparator outputs can be changed using the c2inv and c1inv bits (cmcon<5:4>). ? + v in + v in - output output v in - v in + note 1: when reading the port register, all pins configured as analog inputs will read as a ? 0 ?. pins configured as digital inputs will convert an analog input according to the schmitt trigger input specification. 2: analog levels on any pin defined as a dig- ital input may cause the input buffer to consume more current than is specified.
pic18f6310/6410/8310/8410 ds39635a-page 258 preliminary ? 2004 microchip technology inc. figure 20-3: comparator output block diagram 20.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that occurred. the cmif bit (pir2<6>) is the comparator interrupt flag. the cmif bit must be reset by clearing it. since it is also possible to write a ? 1 ? to this register, a simulated interrupt may be initiated. both the cmie bit (pie2<6>) and the peie bit (intcon<6>) must be set to enable the interrupt. in addition, the gie bit (intcon<7>) must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon will end the mismatch condition. b) clear flag bit cmif. a mismatch condition will continue to set flag bit cmif. reading cmcon will end the mismatch condition and allow flag bit cmif to be cleared. 20.7 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional, if enabled. this interrupt will wake-up the device from sleep mode, when enabled. while the comparator is powered up, higher sleep currents than shown in the power-down current specification will occur. each operational comparator will consume additional current, as shown in the comparator specifications. to minimize power consumption while in sleep mode, turn off the comparators (cm2:cm0 = 111 ) before entering sleep. if the device wakes up from sleep, the contents of the cmcon register are not affected. 20.8 effects of a reset a device reset forces the cmcon register to its reset state, causing the comparator module to be in the comparator reset mode (cm2:cm0 = 000) . this ensures that all potential inputs are analog inputs. device current is minimized when analog inputs are present at reset time. the comparators are powered down during the reset interval. dq en to rf2 or rf1 pin bus data set multiplex cmif bit -+ port pins read cmcon reset from other comparator cxinv dq en cl note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir registers) interrupt flag may not get set.
? 2004 microchip technology inc. preliminary ds39635a-page 259 pic18f6310/6410/8310/8410 20.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 20-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up condition may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. figure 20-4: comparator analog input model table 20-1: registers associated with comparator module va r s < 10k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance va = analog voltage comparator input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 59 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 59 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir2 oscfif cmif ? ? bclif hlvdif tmr3if ccp2if 59 pie2 ocsfie cmie ? ? bclie hlvdie tmr3ie ccp2ie 59 ipr2 oscfip cmip ? ? bclip hlvdip tmr3ip ccp2ip 59 portf read portf pins, write latf latch 60 latf latf data output register 60 trisf portf data direction register 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are unused by the comparator module.
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? 2004 microchip technology inc. preliminary ds39635a-page 261 pic18f6310/6410/8310/8410 21.0 comparator voltage reference module the comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. a block diagram is of the module shown in figure 21-1. the resistor ladder is segmented to provide two ranges of cv ref values and has a power-down function to conserve power when the reference is not being used. the module?s supply reference can be provided from either device v dd /v ss , or an external voltage reference. 21.1 configuring the comparator voltage reference the voltage reference module is controlled through the cvrcon register (register 21-1). the comparator voltage reference provides two ranges of output volt- age, each with 16 distinct levels. the range to be used is selected by the cvrr bit (cvrcon<5>). the primary difference between the ranges is the size of the steps selected by the cv ref selection bits (cvr3:cvr0), with one range offering finer resolution. the equations used to calculate the output of the comparator voltage reference are as follows: if cvrr = 1 : cv ref = ((cvr3:cvr0)/24) x cv rsrc if cvrr = 0 : cv ref = (cv dd x 1/4) + (((cvr3:cvr0)/32) x cv rsrc ) the comparator reference supply voltage can come from either v dd and v ss , or the external v ref + and v ref - that are multiplexed with ra2 and ra3. the voltage source is selected by the cvrss bit (cvrcon<4>). the settling time of the comparator voltage reference must be considered when changing the cv ref output (see table 26-3 in section 26.0 ?electrical characteristics? ). register 21-1: cvrcon register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe (1) cvrr cvrss cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 bit 7 cvren : comparator voltage reference enable bit 1 = cv ref circuit powered on 0 = cv ref circuit powered down bit 6 cvroe : comparator v ref output enable bit (1) 1 = cv ref voltage level is also output on the rf5/an10/cv ref pin 0 = cv ref voltage is disconnected from the rf5/an10/cv ref pin note 1: cvroe overrides the trisf<5> bit setting if enabled for output; rf5 must also be configured as an input by setting trisf<5> to ? 1 ?. bit 5 cvrr : comparator v ref range selection bit 1 = 0.00 cv rsrc to 0.75 cv rsrc , with cv rsrc /24 step size 0 = 0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size bit 4 cvrss : comparator v ref source selection bit 1 = comparator reference source, cv rsrc = (v ref +) ? (v ref -) 0 = comparator reference source, cv rsrc = v dd ? v ss bit 3-0 cvr3:cvr0: comparator v ref value selection bits (0 (cvr3:cvr0) 15) when cvrr = 1 : cv ref = ((cvr3:cvr0)/24) ? (cv rsrc ) when cvrr = 0 : cv ref = (cv rsrc /4) + ((cvr3:cvr0)/32) ? (cv rsrc ) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 262 preliminary ? 2004 microchip technology inc. figure 21-1: voltage reference block diagram 21.2 voltage reference accuracy/error the full range of voltage reference cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 21-1) keep cv ref from approaching the refer- ence source rails. the voltage reference is derived from the reference source; therefore, the cv ref output changes with fluctuations in that source. the tested absolute accuracy of the voltage reference can be found in section 26.0 ?electrical characteristics? . 21.3 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the cvrcon register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 21.4 effects of a reset a device reset disables the voltage reference by clearing bit cvren (cvrcon<7>). this reset also disconnects the reference from the ra2 pin by clearing bit cvroe (cvrcon<6>) and selects the high-voltage range by clearing bit cvrr (cvrcon<5>). the cvr value select bits are also cleared. 21.5 connection considerations the voltage reference module operates independently of the comparator module. the output of the reference generator may be connected to the rf5 pin if the trisf<5> bit and the cvroe bit are both set. enabling the voltage reference output onto the rf5 pin, with an input signal present, will increase current con- sumption. connecting rf5 as a digital output with cvrss enabled will also increase current consumption. the rf5 pin can be used as a simple d/a output with limited drive capability. due to the limited current drive capability, a buffer must be used on the voltage refer- ence output for external connections to v ref . figure 21-2 shows an example buffering technique. 16 to 1 mux cvr3:cvr0 8r r cvren cvrss = 0 v dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 r r r r r r 16 steps cvrr cv ref
? 2004 microchip technology inc. preliminary ds39635a-page 263 pic18f6310/6410/8310/8410 figure 21-2: voltage reference output buffer example table 21-1: registers associated with the comparator voltage reference cv ref output + ? cv ref module voltage reference output impedance r (1) rf5 note 1: r is dependent upon the voltage reference configuration bits, cvrcon<3:0> and cvrcon<5>. pic18fxxxx name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 59 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 59 trisf portf data direction register 60 legend: shaded cells are not used with the comparator voltage reference.
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? 2004 microchip technology inc. preliminary ds39635a-page 265 pic18f6310/6410/8310/8410 22.0 high/low-voltage detect (hlvd) pic18f6310/6410/8310/8410 devices have a high/low-voltage detect module (hlvd). this is a programmable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point. if the device experiences an excursion past the trip point in that direction, an inter- rupt flag is set. if the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. the high/low-voltage detect control register (register 22-1) completely controls the operation of the hlvd module. this allows the circuitry to be ?turned off? by the user under software control, which minimizes the current consumption for the device. the block diagram for the hlvd module is shown in figure 22-1. register 22-1: hlvdcon: high/low-voltage de tect control register r/w-0 u-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 vdirmag ? irvst hlvden hlvdl3 hlvdl2 hlvdl1 hlvdl0 bit 7 bit 0 bit 7 vdirmag: voltage direction magnitude select bit 1 = event occurs when voltage equals or exceeds trip point (hlvdl3:hldvl0) 0 = event occurs when voltage equals or falls below trip point (hlvdl3:hlvdl0) bit 6 unimplemented: read as ? 0 ? bit 5 irvst: internal reference voltage stable flag bit 1 = indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the hlvd interrupt should not be enabled bit 4 hlvden: high/low-voltage detect power enable bit 1 = hlvd enabled 0 = hlvd disabled bit 3-0 hlvdl3:hlvdl0: voltage detection limit bits 1111 = external analog input is used (input comes from the hlvdin pin) 1110 = 4.41v-4.87v 1101 = 4.11v-4.55v 1100 = 3.92v-4.34v 1011 = 3.72v-4.12v 1010 = 3.53v-3.91v 1001 = 3.43v-3.79v 1000 = 3.24v-3.58v 0111 = 2.95v-3.26v 0110 = 2.75v-3.03v 0101 = 2.64v-2.92v 0100 = 2.43v-2.69v 0011 = 2.35v-2.59v 0010 = 2.16v-2.38v 0001 = 1.96v-2.16v 0000 = reserved note: hlvdl3:hlvdl0 modes that result in a trip point below the valid operating voltage of the device are not tested. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f6310/6410/8310/8410 ds39635a-page 266 preliminary ? 2004 microchip technology inc. the module is enabled by setting the hlvden bit. each time that the hlvd module is enabled, the circuitry requires some time to stabilize. the irvst bit is a read-only bit and is used to indicate when the circuit is stable. the module can only generate an interrupt after the circuit is stable and irvst is set. the vdirmag bit determines the overall operation of the module. when vdirmag is cleared, the module monitors for drops in v dd below a predetermined set point. when the bit is set, the module monitors for rises in v dd above the set point. 22.1 operation when the hlvd module is enabled, a comparator uses an internally generated reference voltage as the set point. the set point is compared with the trip point where each node in the resistor divider represents a trip point voltage. the ?trip point? voltage is the voltage level at which the device detects a high or low-voltage event, depending on the configuration of the module. when the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. the comparator then generates an interrupt signal by setting the hlvdif bit. the trip point voltage is software programmable to any one of 16 values. the trip point is selected by programming the hlvdl3:hlvdl0 bits (hlvdcon<3:0>). the hlvd module has an additional feature that allows the user to supply the trip voltage to the module from an external source. this mode is enabled when bits hlvdl3:hlvdl0 are set to ? 1111 ?. in this state, the comparator input is multiplexed from the external input pin, hlvdin. this gives users flexibility because it allows them to configure the high/low-voltage detect interrupt to occur at any voltage in the valid operating range. figure 22-1: hlvd module block diagram (with external input) set v dd 16 to 1 mux hlvden hlvdcon hlvdin hlvdl3:hlvdl0 register hlvdin v dd externally generated trip point hlvdif hlvden boren internal voltage reference vdirmag
? 2004 microchip technology inc. preliminary ds39635a-page 267 pic18f6310/6410/8310/8410 22.2 hlvd setup the following steps are needed to set up the hlvd module: 1. disable the module by clearing the hlvden bit (hlvdcon<4>). 2. write the value to the hlvdl3:hlvdl0 bits that selects the desired hlvd trip point. 3. set the vdirmag bit to detect high voltage (vdirmag = 1 ) or low voltage (vdirmag = 0 ). 4. enable the hlvd module by setting the hlvden bit. 5. clear the hlvd interrupt flag (pir2<2>), which may have been set from a previous interrupt. 6. enable the hlvd interrupt, if interrupts are desired, by setting the hlvdie and gie bits (pie<2> and intcon<7>). an interrupt will not be generated until the irvst bit is set. 22.3 current consumption when the module is enabled, the hlvd comparator and voltage divider are enabled and will consume static current. the total current consumption, when enabled, is specified in electrical specification parameter #d022b. depending on the application, the hlvd module does not need to be operating constantly. to decrease the current requirements, the hlvd circuitry may only need to be enabled for short periods where the voltage is checked. after doing the check, the hlvd module may be disabled. 22.4 hlvd start-up time the internal reference voltage of the hlvd module, specified in electrical specification parameter #d423, may be used by other internal circuitry, such as the programmable brown-out reset. if the hlvd or other circuits using the voltage reference are disabled to lower the device?s current consumption, the reference voltage circuit will require time to become stable before a low or high-voltage condition can be reliably detected. this start-up time, t irvst , is an interval that is independent of device clock speed. it is specified in electrical specification parameter 36 (table 26-12). the hlvd interrupt flag is not enabled until t irvst has expired and a stable reference voltage is reached. for this reason, brief excursions beyond the set point may not be detected during this interval. refer to figure 22-2 or figure 22-3. figure 22-2: high/low-voltage detect operation (vdirmag = 0 ) v lvd v dd hlvdif v lvd v dd enable hlvd t ivrst hlvdif may not be set enable hlvd hlvdif hlvdif cleared in software hlvdif cleared in software hlvdif cleared in software, case 1: case 2: hlvdif remains set since hlvd condition still exists t ivrst internal reference is stable internal reference is stable irvst irvst
pic18f6310/6410/8310/8410 ds39635a-page 268 preliminary ? 2004 microchip technology inc. figure 22-3: high/low-voltage detect operation (vdirmag = 1 ) 22.5 applications in many applications, the ability to detect a drop below or rise above a particular threshold is desirable. for example, the hlvd module could be periodically enabled to detect usb attach or detach. this assumes the device is powered by a lower voltage source than the universal serial bus when detached. an attach would indicate a high-voltage detect from, for example, 3.3v to 5v (the voltage on usb) and vice versa for a detach. this feature could save a design a few extra components and an attach signal (input pin). for general battery applications, figure 22-4 shows a possible voltage curve. over time, the device voltage decreases. when the device voltage reaches voltage v a , the hlvd logic generates an interrupt at time t a . the interrupt could cause the execution of an isr, which would allow the application to perform ?house- keeping tasks? and perform a controlled shutdown before the device voltage exits the valid operating range at t b . the hlvd thus would give the application a time window, represented by the difference between t a and t b , to safely exit. figure 22-4: typical low-voltage detect application v lvd v dd hlvdif v lvd v dd enable hlvd t ivrst hlvdif may not be set enable hlvd hlvdif hlvdif cleared in software hlvdif cleared in software hlvdif cleared in software, case 1: case 2: hlvdif remains set since hlvd condition still exists t ivrst irvst internal reference is stable internal reference is stable irvst time voltage v a v b t a t b v a = hlvd trip point v b = minimum valid device operating voltage legend:
? 2004 microchip technology inc. preliminary ds39635a-page 269 pic18f6310/6410/8310/8410 22.6 operation during sleep when enabled, the hlvd circuitry continues to operate during sleep. if the device voltage crosses the trip point, the hlvdif bit will be set and the device will wake-up from sleep. device execution will continue from the interrupt vector address if interrupts have been globally enabled. 22.7 effects of a reset a device reset forces all registers to their reset state. this forces the hlvd module to be turned off. table 22-1: registers associated with high/low-voltage detect module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page hlvdcon vdirmag ? irvst hlvden hlvdl3 hlvdl2 hlvdl1 hlvdl0 58 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 57 pir2 oscfif cmif ? ? bclif hlvdif tmr3if ccp2if 59 pie2 ocsfie cmie ? ? bclie hlvdie tmr3ie ccp2ie 59 ipr2 oscfip cmip ? ? bclip hlvdip tmr3ip ccp2ip 59 legend: ? = unimplemented, read as ? 0 ?. shaded cells are unused by the hlvd module.
pic18f6310/6410/8310/8410 ds39635a-page 270 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 271 pic18f6310/6410/8310/8410 23.0 special features of the cpu pic18f6310/6410/8310/8410 devices include several features intended to maximize reliability and minimize cost through elimination of external components. these are: oscillator selection resets: - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) fail-safe clock monitor two-speed start-up code protection id locations in-circuit serial programming the oscillator can be configured for the application depending on frequency, power, accuracy and cost. all of the options are discussed in detail in section 2.0 ?oscillator configurations? . a complete discussion of device resets and interrupts is available in previous sections of this data sheet. in addition to their power-up and oscillator start-up tim- ers provided for resets, pic18f6310/6410/8310/8410 devices have a watchdog timer, which is either permanently enabled via the configuration bits, or software controlled (if configured as disabled). the inclusion of an internal rc oscillator also provides the additional benefits of a fail-safe clock monitor (fscm) and two-speed start-up. fscm provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. two-speed start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. all of these features are enabled and configured by setting the appropriate configuration register bits. 23.1 configuration bits the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ? 1 ?), to select various device configurations. these bits are mapped starting at program memory location 300000h. the user will note that address 300000h is beyond the user program memory space. in fact, it belongs to the configuration memory space (300000h-3fffffh), which can only be accessed using table reads. table 23-1: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300001h config1h ieso fcmen ? ? fosc3 fosc2 fosc1 fosc0 00-- 0111 300002h config2l ? ? ? borv1 borv0 boren1 boren0 pwrten ---1 1111 300003h config2h ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 wdten ---1 1111 300004h config3l wait bw ? ? ? ?pm1pm0 11-- --11 300005h config3h mclre ? ? ? ?lpt1osc ? ccp2mx 1--- -0-1 300006h config4l debug xinst ? ? ? ? ?stvren 10-- ---1 300008h config5l ? ? ? ? ? ? ?cp ---- ---1 30000ch config7l (1) ? ? ? ? ? ? ?ebtr ---- ---1 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 11qx xxxx (2) 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0000 qq1q (2) legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on individual device. shaded cells are unimplemented, read as ? 0 ?. note 1: unimplemented in pic18f6310/6410 devices; maintain this bit set. 2: see register 23-9 for devid1 values. devid register s are read-only and cannot be programmed by the user.
pic18f6310/6410/8310/8410 ds39635a-page 272 preliminary ? 2004 microchip technology inc. register 23-1: config1h: configuration register 1 high (byte address 300001h) r/p-0 r/p-0 u-0 u-0 r/p-0 r/p-1 r/p-1 r/p-1 ieso fcmen ? ? fosc3 fosc2 fosc1 fosc0 bit 7 bit 0 bit 7 ieso: internal/external oscillator switchover bit 1 = oscillator switchover mode enabled 0 = oscillator switchover mode disabled bit 6 fcmen: fail-safe clock monitor enable bit 1 = fail-safe clock monitor enabled 0 = fail-safe clock monitor disabled bit 5-4 unimplemented: read as ? 0 ? bit 3-0 fosc3:fosc0: oscillator selection bits 11xx = external rc oscillator, clko function on ra6 101x = external rc oscillator, clko function on ra6 1001 = internal oscillator block, clko function on ra6, port function on ra7 1000 = internal oscillator block, port function on ra6 and ra7 0111 = external rc oscillator, port function on ra6 0110 = hs oscillator, pll enabled (clock frequency = 4 x fosc1) 0101 = ec oscillator, port function on ra6 0100 = ec oscillator, clko function on ra6 0011 = external rc oscillator, clko function on ra6 0010 = hs oscillator 0001 = xt oscillator 0000 = lp oscillator legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2004 microchip technology inc. preliminary ds39635a-page 273 pic18f6310/6410/8310/8410 register 23-2: config2l: configuration register 2 low (byte address 300002h) u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? borv1 borv0 boren1 (1) boren0 (1) pwrten (1) bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4-3 borv1:borv0: brown-out reset voltage bits 11 = v bor set to 2.1v 10 = v bor set to 2.8v 01 = v bor set to 4.3v 00 = v bor set to 4.6v bit 2-1 boren1:boren0 brown-out reset enable bits (1) 11 = brown-out reset enabled in hardware only (sboren is disabled) 10 = brown-out reset enabled in hardware only and disabled in sleep mode (sboren is disabled) 10 = brown-out reset enabled and controlled by software (sboren is enabled) 10 = brown-out reset disabled in hardware and software bit 0 pwrten : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled note 1: the power-up timer is decoupled from brown-out reset, allowing these features to be independently controlled. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
pic18f6310/6410/8310/8410 ds39635a-page 274 preliminary ? 2004 microchip technology inc. register 23-3: config2h: configuration register 2 high (byte address 300003h) u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 wdten bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4-1 wdtps3:wdtps0: watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 wdten: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on the swdten bit) legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2004 microchip technology inc. preliminary ds39635a-page 275 pic18f6310/6410/8310/8410 register 23-4: config3l: conf iguration register 3 low (byte address 300004h) register 23-5: config3h: configuration register 3 high (byte address 300005h) r/p-1 r/p-1 u-0 u-0 u-0 u-0 r/p-1 r/p-1 wait bw ? ? ? ?pm1pm0 bit 7 bit 0 bit 7 wait: external bus data wait enable bit 1 = wait selections unavailable, device will not wait 0 = wait programmed by wait1 and wait0 bits of memcom register (memcom<5:4>) bit 6 bw: external bus data width select bit 1 = 16-bit external bus data width 0 = 8-bit external bus data width bit 5-2 unimplemented: read as ? 0 ? bit 1-0 pm1:pm0: processor data memory mode select bits 11 = microcontroller mode 10 = microprocessor mode (1) 01 = microcontroller with boot block mode (1) 00 = extended microcontroller mode (1) note 1: this mode is available only on pic18f8310/8410 devices. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value after erase ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/p-1 u-0 u-0 u-0 u-0 r/p-0 u-0 r/p-1 mclre ? ? ? ?lpt1osc ? ccp2mx bit 7 bit 0 bit 7 mclre: mclr pin enable bit 1 = mclr pin enabled; rg5 input pin disabled 0 = rg5 input pin enabled; mclr disabled bit 6-3 unimplemented: read as ? 0 ? bit 2 lpt1osc: low-power timer 1 oscillator enable bit 1 = timer1 configured for low-power operation 0 = timer1 configured for higher power operation bit 1 unimplemented: read as ? 0 ? bit 0 ccp2mx: ccp2 mux bit in microcontroller mode only (all devices): 1 = ccp2 input/output is multiplexed with rc1 0 = ccp2 input/output is multiplexed with re7 in microprocessor, extended microcontroller and microcontroller with boot block modes (pic18f8310/8410 devices only): 1 = ccp2 input/output is multiplexed with rc1 0 = ccp2 input/output is multiplexed with rb3 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
pic18f6310/6410/8310/8410 ds39635a-page 276 preliminary ? 2004 microchip technology inc. register 23-6: config4l: configuration register 4 low (byte address 300006h) register 23-7: config5l: configuration register 5 low (byte address 300008h) r/p-1 r/p-0 u-0 u-0 u-0 u-0 u-0 r/p-1 debug xinst ? ? ? ? ?stvren bit 7 bit 0 bit 7 debug : background debugger enable bit 1 = background debugger disabled, rb6 and rb7 configured as general purpose i/o pins 0 = background debugger enabled, rb6 and rb7 are dedicated to in-circuit debug bit 6 xinst: extended instruction set enable bit 1 = instruction set extension and indexed addressing mode enabled 0 = instruction set extension and indexed addressing mode disabled (legacy mode) bit 5-1 unimplemented: read as ? 0 ? bit 0 stvren: stack full/underflow reset enable bit 1 = stack full/underflow will cause reset 0 = stack full/underflow will not cause reset legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/c-1 ? ? ? ? ? ? ?cp bit 7 bit 0 bit 7-1 unimplemented: read as ? 0 ? bit 0 cp: code protection bit 1 = program memory block not code-protected 0 = program memory block code-protected legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2004 microchip technology inc. preliminary ds39635a-page 277 pic18f6310/6410/8310/8410 register 23-8: config7l: configuration register 7 low (byte address 30000ch) (1) u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/c-1 ? ? ? ? ? ? ? ebtr (2) bit 7 bit 0 bit 7-1 unimplemented: read as ? 0 ? bit 0 ebtr: table read protection bit (2) 1 = internal program memory block not protected from table reads executed from external memory block 0 = internal program memory block protected from table reads executed from external memory block note 1: unimplemented on pic18f6310/6410 devices; maintain the bit set. 2: valid for the entire internal program memory block in extended microcontroller mode and for only the boot block (0000h to 07ffh) in microcontroller with boot block mode. this bit has no effect in microcontroller and microprocessor modes. legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
pic18f6310/6410/8310/8410 ds39635a-page 278 preliminary ? 2004 microchip technology inc. register 23-9: device id register 1 for pic18f6310/6410/8310/8410 devices register 23-10: device id register 2 for pic18f6310/6410/8310/8410 devices rrrrrrrr dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 bit 7-5 dev2:dev0: device id bits 110 = pic18f8310, pic18f8410 111 = pic18f6310, pic18f6410 note: these values for dev2:dev0 may be shared with other devices. the specific device is always identified by using the entire dev10:dev0 bit sequence. bit 4-0 rev4:rev0: revision id bits these bits are used to indicate the device revision. legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state rrrrrrrr dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 bit 7 bit 0 bit 7-0 dev10:dev3: device id bits these bits are used with the dev2:dev0 bits in the device id register 1 to identify the part number. 0000 0110 = pic18f6410/8410 devices 0000 1011 = pic18f6310/8310 devices note: these values for dev10:dev3 may be shared with other devices. the specific device is always identified by using the entire dev10:dev0 bit sequence. legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state
? 2004 microchip technology inc. preliminary ds39635a-page 279 pic18f6310/6410/8310/8410 23.2 watchdog timer (wdt) for pic18f6310/6410/8310/8410 devices, the wdt is driven by the intrc source. when the wdt is enabled, the clock source is also enabled. the nominal wdt period is 4 ms and has the same stability as the intrc oscillator. the 4 ms period of the wdt is multiplied by a 16-bit postscaler. any output of the wdt postscaler is selected by a multiplexer, controlled by bits in configu- ration register 2h. available periods range from 4 ms to 131.072 seconds (2.18 minutes). the wdt and postscaler are cleared when any of the following events occur: a sleep or clrwdt instruction is executed, the ircf bits (osccon<6:4>) are changed or a clock failure has occurred. 23.2.1 control register register 23-11 shows the wdtcon register. this is a readable and writable register, which contains a control bit that allows software to override the wdt enable configuration bit, but only if the configuration bit has disabled the wdt. figure 23-1: wdt block diagram note 1: the clrwdt and sleep instructions clear the wdt and postscaler counts when executed. 2: changing the setting of the ircf bits (osccon<6:4>) clears the wdt and postscaler counts. 3: when a clrwdt instruction is executed the postscaler count will be cleared. intrc source wdt wake-up reset wdt wdt counter programmable postscaler 1:1 to 1:32,768 enable wdt wdtps<3:0> swdten wdten clrwdt 4 from power reset all device resets sleep intrc control 128 change on ircf bits managed modes
pic18f6310/6410/8310/8410 ds39635a-page 280 preliminary ? 2004 microchip technology inc. register 23-11: wdtcon: watchdog timer control register table 23-2: summary of watchdog timer registers u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?swdten bit 7 bit 0 bit 7-1 unimplemented : read as ? 0 ? bit 0 swdten: software controlled watchdog timer enable bit 1 = watchdog timer is on 0 = watchdog timer is off note: this bit has no effect if the configuration bit wdten is enabled. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por name bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 reset values on page rcon ipen sboren ? ri to pd por bor 58 wdtcon ? ? ? ? ? ? ?swdten58 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the watchdog timer.
? 2004 microchip technology inc. preliminary ds39635a-page 281 pic18f6310/6410/8310/8410 23.3 two-speed start-up the two-speed start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the intrc oscillator as a clock source until the primary clock source is available. it is enabled by setting the ieso configuration bit. two-speed start-up should be enabled only if the primary oscillator mode is lp, xt, hs or hspll (crystal-based modes). other sources do not require a ost start-up delay; for these, two-speed start-up should be disabled. when enabled, resets and wake-ups from sleep mode cause the device to configure itself to run from the inter- nal oscillator block as the clock source, following the time-out of the power-up timer after a power-on reset is enabled. this allows almost immediate code execution while the primary oscillator starts and the ost is running. once the ost times out, the device automatically switches to pri_run mode. because the osccon register is cleared on reset events, the intosc (or postscaler) clock source is not initially available after a reset event; the intrc clock is used directly at its base frequency. to use a higher clock speed on wake-up, the intosc or postscaler clock sources can be selected to provide a higher clock speed by setting bits, ifrc2:ifrc0, immediately after reset. for wake-ups from sleep, the intosc or postscaler clock sources can be selected by setting the ifrc2:ifrc0 bits prior to entering sleep mode. in all other power managed modes, two-speed start-up is not used. the device will be clocked by the currently selected clock source until the primary clock source becomes available. the setting of the ieso bit is ignored. 23.3.1 special considerations for using two-speed start-up while using the intrc oscillator in two-speed start-up, the device still obeys the normal command sequences for entering power managed modes, including serial sleep instructions (refer to section 3.1.2 ?entering power managed modes? ). in practice, this means that user code can change the scs1:scs0 bit settings or issue sleep instructions before the ost times out. this would allow an application to briefly wake-up, perform routine ?housekeeping? tasks and return to sleep before the device starts to operate from the primary oscillator. user code can also check if the primary clock source is currently providing the device clocking by checking the status of the osts bit (osccon<3>). if the bit is set, the primary oscillator is providing the clock. otherwise, the internal oscillator block is providing the clock during wake-up from reset or sleep mode. figure 23-2: timing transition for two-speed start-up (intosc to hspll) q1 q3 q4 osc1 peripheral program pc pc + 2 intosc pll clock q1 pc + 6 q2 output q3 q4 q1 cpu clock pc + 4 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. wake from interrupt event t pll (1) 12 n-1n clock osts bit set transition multiplexer t ost (1)
pic18f6310/6410/8310/8410 ds39635a-page 282 preliminary ? 2004 microchip technology inc. 23.4 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. the fscm function is enabled by setting the fcmen configuration bit. when fscm is enabled, the intrc oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure. clock monitoring (shown in figure 23-3) is accomplished by creating a sample clock signal, which is the intrc output divided by 64. this allows ample time between fscm sample clocks for a peripheral clock edge to occur. the peripheral device clock and the sample clock are presented as inputs to the clock monitor latch (cm). the cm is set on the falling edge of the device clock source, but cleared on the rising edge of the sample clock. figure 23-3: fscm block diagram clock failure is tested for on the falling edge of the sam- ple clock. if a sample clock falling edge occurs while cm is still set, a clock failure has been detected (figure 23-4). this causes the following: the fscm generates an oscillator fail interrupt by setting bit, oscfif (pir2<7>); the device clock source is switched to the internal oscillator block (osccon is not updated to show the current clock source ? this is the fail-safe condition); and the wdt is reset. during switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. in these cases, it may be desirable to select another clock configuration and enter an alternate power managed mode. this can be done to attempt a partial recovery or execute a controlled shut- down. see section 3.1.2 ?entering power managed modes? and section 23.3.1 ?special considerations for using two-speed start-up? for more details. to use a higher clock speed on wake-up, the intosc or postscaler clock sources can be selected to provide a higher clock speed by setting bits ifrc2:ifrc0 immediately after reset. for wake-ups from sleep, the intosc or postscaler clock sources can be selected by setting the ifrc2:ifrc0 bits prior to entering sleep mode. the fscm will detect failures of the primary or second- ary clock sources only. if the internal oscillator block fails, no failure would be detected, nor would any action be possible. 23.4.1 fscm and the watchdog timer both the fscm and the wdt are clocked by the intrc oscillator. since the wdt operates with a separate divider and counter, disabling the wdt has no effect on the operation of the intrc oscillator when the fscm is enabled. as already noted, the clock source is switched to the intosc clock when a clock failure is detected. depending on the frequency selected by the ircf2:ircf0 bits, this may mean a substantial change in the speed of code execution. if the wdt is enabled with a small prescale value, a decrease in clock speed allows a wdt time-out to occur and a subsequent device reset. for this reason, fail-safe clock events also reset the wdt and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. 23.4.2 exiting fail-safe operation the fail-safe condition is terminated by either a device reset or by entering a power managed mode. on reset, the controller starts the primary clock source specified in configuration register 1h (with any required start-up delays that are required for the oscil- lator mode, such as the ost or pll timer). the intosc multiplexer provides the device clock until the primary clock source becomes ready (similar to a two-speed start-up). the clock source is then switched to the primary clock (indicated by the osts bit in the osccon register becoming set). the fail-safe clock monitor then resumes monitoring the peripheral clock. the primary clock source may never become ready during start-up. in this case, operation is clocked by the intosc multiplexer. the osccon register will remain in its reset state until a power managed mode is entered. peripheral intrc 64 s c q (32 s) 488 hz (2.048 ms) clock monitor latch (cm) (edge-triggered) clock failure detected source clock q
? 2004 microchip technology inc. preliminary ds39635a-page 283 pic18f6310/6410/8310/8410 figure 23-4: fscm timing diagram 23.4.3 fscm interrupts in power managed modes by entering a power managed mode, the clock multiplexer selects the clock source selected by the osccon register. fail-safe monitoring of the power managed clock source resumes in the power managed mode. if an oscillator failure occurs during power managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. if enabled (oscfif = 1 ), code execution will be clocked by the intosc multiplexer. an automatic transition back to the failed clock source will not occur. if the interrupt is disabled, the device will not exit the power managed mode on oscillator failure. instead, the device will continue to operate as before, but clocked by the intosc multiplexer. while in idle mode, subse- quent interrupts will cause the cpu to begin executing instructions while being clocked by the intosc multiplexer. 23.4.4 por or wake from sleep the fscm is designed to detect oscillator failure at any point after the device has exited power-on reset (por) or low-power sleep mode. when the primary device clock is ec, rc or intrc modes, monitoring can begin immediately following these events. for oscillator modes involving a crystal or resonator (hs, hspll, lp or xt), the situation is somewhat different. since the oscillator may require a start-up time considerably longer than the fcsm sample clock time, a false clock failure may be detected. to prevent this, the internal oscillator block is automatically config- ured as the device clock and functions until the primary clock is stable (the ost and pll timers have timed out). this is identical to two-speed start-up mode. once the primary clock is stable, the intrc returns to its role as the fscm source. as noted in section 23.3.1 ?special considerations for using two-speed start-up? , it is also possible to select another clock configuration and enter an alternate power managed mode while waiting for the primary clock to become stable. when the new powered managed mode is selected, the primary clock is disabled. oscfif cm output device clock output sample clock failure detected oscillator failure note: the device clock is normally at a mu ch higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q ) cm test cm test cm test note: the same logic that prevents false oscillator failure interrupts on por or wake from sleep, will also prevent the detection of the oscillator?s failure to start at all following these events. this can be avoided by monitoring the osts bit and using a timing routine to determine if the oscillator is taking too long to start. even so, no oscillator failure interrupt will be flagged.
pic18f6310/6410/8310/8410 ds39635a-page 284 preliminary ? 2004 microchip technology inc. 23.5 program verification and code protection the overall structure of the code protection on the pic18f6310/6410/8310/8410 flash devices differs from previous pic18 devices. for all devices in the pic18fx310/x410 family, the user program memory is made of a single block. figure 23-5 shows the program memory organization for individual devices. code protection for this block is controlled by a single bit, cp (config5l<0>). the cp bit inhibits external reads and writes. it has no direct effect in normal execution mode. 23.5.1 code protection from external table reads the program memory may be read to any location using the table read instructions. the device id and the configuration registers may be read with the table read instructions. for devices with the external memory interface, it is possible to execute a table read from an external program memory space and read the contents of the on-chip memory. an additional code protection bit, ebtr (config7l<0>), is used to protect the on-chip program memory space from this possibility. setting ebtr prevents table read commands from executing on any address in the on-chip program memory space. ebtr is implemented only on devices with the external memory interface. its operation also depends on the particular mode of operation selected. in extended microcontroller mode, programming ebtr enables protection from external table reads for the entire program memory. in microcontroller with boot block mode, only the first 2 kbytes of on-chip memory (000h to 7ffh) are protected; this is because only this range of internal program memory is accessible by the microcontroller in this operating mode. when the device is in micrcontroller or microprocessor modes, ebtr has no effect on code protection. 23.5.2 configuration register protection the configuration registers can only be written via icsp using an external programmer. no separate protection bit is associated with them. figure 23-5: code-protected program memory for pic18f6310/6410/8310/8410 table 23-3: summary of code protection registers memory size/device block code protection controlled by: 8kbytes (pic18f6310/8310) address range 16 kbytes (pic18f6410/8410) address range program memory block 000000h 001fffh program memory block 000000h 003fffh cp, ebtr unimplemented read ? 0 ?s 002000h 1fffffh unimplemented read ? 0 ?s 004000h 1fffffh (unimplemented memory space) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 300008h config5l ? ? ? ? ? ? ?cp 30000ch config7l* ? ? ? ? ? ? ? ebtr legend: shaded cells are unimplemented. * unimplemented in pic18f6310/8310 devices; maintain this bit set.
? 2004 microchip technology inc. preliminary ds39635a-page 285 pic18f6310/6410/8310/8410 23.6 id locations eight memory locations (200000h-200007h) are designated as id locations, where the user can store checksum or other code identification numbers. these locations are readable during normal execution through the tblrd instruction; during program/verify, these locations are readable and writable. the id locations can be read when the device is code-protected. 23.7 in-circuit serial programming pic18f6310/6410/8310/8410 microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. this allows customers to manu- facture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 23.8 in-circuit debugger when the debug configuration bit is programmed to a ? 0 ?, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab ? ide. when the microcontroller has this feature enabled, some resources are not available for general use. table 23-4 shows which resources are required by the background debugger. table 23-4: debugger resources to use the in-circuit debugger function of the micro- controller, the design must implement in-circuit serial programming connections to mclr /v pp , v dd , v ss , rb7 and rb6. this will interface to the in-circuit debugger module available from microchip or one of the third party development tool companies. i/o pins: rb6, rb7 stack: 2 levels program memory: 512 bytes data memory: 10 bytes
pic18f6310/6410/8310/8410 ds39635a-page 286 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 287 pic18f6310/6410/8310/8410 24.0 instruction set summary pic18f6310/6410/8310/8410 devices incorporate the standard set of 75 pic18 core instructions, as well as an extended set of 8 new instructions for the optimiza- tion of code that is recursive or that utilizes a software stack. the extended set is discussed later in this section. 24.1 standard instruction set the standard pic18 instruction set adds many enhancements to the previous picmicro ? instruction sets, while maintaining an easy migration from these picmicro instruction sets. most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: byte-oriented operations bit-oriented operations literal operations control operations the pic18 instruction set summary in table 24-2 lists byte-oriented , bit-oriented , literal and control operations. table 24-1 shows the opcode field descriptions. most byte-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the destination of the result (specified by ?d?) 3. the accessed memory (specified by ?a?) the file register designator ?f? specifies which file register is to be used by the instruction. the destination designator ?d? specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the wreg register. if ?d? is one, the result is placed in the file register specified in the instruction. all bit-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the bit in the file register (specified by ?b?) 3. the accessed memory (specified by ?a?) the bit field designator ?b? selects the number of the bit affected by the operation, while the file register desig- nator ?f? represents the number of the file in which the bit is located. the literal instructions may use some of the following operands: a literal value to be loaded into a file register (specified by ?k?) the desired fsr register to load the literal value into (specified by ?f?) no operand required (specified by ???) the control instructions may use some of the following operands: a program memory address (specified by ?n?) the mode of the call or return instructions (specified by ?s?) the mode of the table read and table write instructions (specified by ?m?) no operand required (specified by ???) all instructions are a single word, except for four double-word instructions. these instructions were made double-word to contain the required information in 32 bits. in the second word, the 4 msbs are ? 1 ?s. if this second word is executed as an instruction (by itself), it will execute as a nop . all single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . the double word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. two-word branch instructions (if true) would take 3 s. figure 24-1 shows the general formats that the instruc- tions can have. all examples use the convention ?nnh? to represent a hexadecimal number. the instruction set summary, shown in table 24-2, lists the standard instructions recognized by the microchip assembler (mpasm?). section 24.1.1 ?standard instruction set? provides a description of each instruction.
pic18f6310/6410/8310/8410 ds39635a-page 288 preliminary ? 2004 microchip technology inc. table 24-1: opcode field descriptions field description a ram access bit a = 0 : ram location in access ram (bsr register is ignored) a = 1 : ram bank is specified by bsr register bbb bit address within an 8-bit file register (0 to 7). bsr bank select register. used to select the current ram bank. c, dc, z, ov, n alu status bits: c arry, d igit c arry, z ero, ov erflow, n egative. d destination select bit d = 0 : store result in wreg d = 1 : store result in file register f. dest destination: either the wreg register or the specified register file location. f 8-bit register file address (00h to ffh) , or 2-bit fsr designator (0h to 3h). f s 12-bit register file address (000h to f ffh). this is the source address. f d 12-bit register file address (000h to fffh). this is the destination address. gie global interrupt enable bit. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label label name. mm the mode of the tblptr register for the table read and table write instructions. only used with table read and table write instructions: * no change to register (such as tblptr with table reads and writes). *+ post-increment register (such as tblptr with table reads and writes). *- post-decrement register (such as tblptr with table reads and writes). +* pre-increment register (such as tblptr with table reads and writes). n the relative address (2?s complement number) for rela tive branch instructions, or the direct address for call/branch and return instructions. pc program counter. pcl program counter low byte. pch program counter high byte. pclath program counter high byte latch. pclatu program counter upper byte latch. pd power-down bit. prodh product of multiply high byte. prodl product of multiply low byte. s fast call/return mode select bit s = 0 : do not update into/from shadow registers s = 1 : certain registers loaded into/from shadow registers (fast mode) tblptr 21-bit table pointer (points to a program memory location). tablat 8-bit table latch. to time-out bit. tos top-of-stack. u unused or unchanged. wdt watchdog timer. wreg working register (accumulator). x don?t care (? 0 ? or ? 1 ?). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. z s 7-bit offset value for indirect addressing of register files (source). z d 7-bit offset value for indirect addre ssing of register files (destination). { } optional argument. [text] indicates an indexed address. (text) the contents of text . [expr] specifies bit n of the register indicated by the pointer expr . assigned to. < > register bit field. in the set of. italics user-defined term (font is courier).
? 2004 microchip technology inc. preliminary ds39635a-page 289 pic18f6310/6410/8310/8410 figure 24-1: general format for instructions byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file register (f) a = 0 to force access bank bit-oriented file register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file register (f) literal operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call, goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file register address control operations example instruction addwf myreg, w, b movff myreg1, myreg2 bsf myreg, bit, b movlw 7fh goto label 15 8 7 0 opcode n<7:0> (literal) 15 12 11 0 1111 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc s
pic18f6310/6410/8310/8410 ds39635a-page 290 preliminary ? 2004 microchip technology inc. table 24-2: pic18fxxx instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s , f d f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination)2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 1, 2 4 1, 2 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: table write instructions are unavailable in 64-pin devices in normal operating modes. see section 6.4 ?writing to program memory space (pic18f8310/8410 only)? and section 6.6 ?writing and erasing on-chip program memory (icsp mode)? for more information.
? 2004 microchip technology inc. preliminary ds39635a-page 291 pic18f6310/6410/8310/8410 bit-oriented operations bcf bsf btfsc btfss btg f, b, a f, b, a f, b, a f, b, a f, d, a bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff none none none none none 1, 2 1, 2 3, 4 3, 4 1, 2 control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep n n n n n n n n n n, s ? ? n ? ? ? ? n s k s ? branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine 1st word 2nd word clear watchdog timer decimal adjust wreg go to address 1st word 2nd word no operation no operation pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c none none none none none none all gie/gieh, peie/giel none none to , pd 4 table 24-2: pic18fxxx instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: table write instructions are unavailable in 64-pin devices in normal operating modes. see section 6.4 ?writing to program memory space (pic18f8310/8410 only)? and section 6.6 ?writing and erasing on-chip program memory (icsp mode)? for more information.
pic18f6310/6410/8310/8410 ds39635a-page 292 preliminary ? 2004 microchip technology inc. literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw k k k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg move literal (12-bit) 2nd word to fsr(f) 1st word move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment ta b l e wr i t e table write with post-increment table write with post-decrement table write with pre-increment 2 2 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 none none none none none none none none 5 5 5 5 table 24-2: pic18fxxx instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop , unless the first word of the instruction retrieves the information embedded in these 16-bits. this ensures that all program memory locations have a valid instruction. 5: table write instructions are unavailable in 64-pin devices in normal operating modes. see section 6.4 ?writing to program memory space (pic18f8310/8410 only)? and section 6.6 ?writing and erasing on-chip program memory (icsp mode)? for more information. note: all pic18 instructions may take an optional label argument, preceding the instruction mnemonic, for use in symbolic addressing. if a label is used, the instruction format then becomes: {label} instruction argument(s)
? 2004 microchip technology inc. preliminary ds39635a-page 293 pic18f6310/6410/8310/8410 24.1.1 standard instruction set addlw add literal to w syntax: addlw k operands: 0 k 255 operation: (w) + k w status affected: n, ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of w are added to the 8-bit literal ?k? and the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: addlw 15h before instruction w = 10h after instruction w = 25h addwf add w to f syntax: addwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) + (f) dest status affected: n, ov, c, dc, z encoding: 0010 01da ffff ffff description: add w to register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed litera l offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: addwf reg, 0, 0 before instruction w = 17h reg = 0c2h after instruction w = 0d9h reg = 0c2h
pic18f6310/6410/8310/8410 ds39635a-page 294 preliminary ? 2004 microchip technology inc. addwfc add w and carry bit to f syntax: addwfc f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) + (f) + (c) dest status affected: n,ov, c, dc, z encoding: 0010 00da ffff ffff description: add w, the carry flag and data memory location ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in data memory location ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: addwfc reg, 0, 1 before instruction carry bit = 1 reg = 02h w=4dh after instruction carry bit = 0 reg = 02h w = 50h andlw and literal with w syntax: andlw k operands: 0 k 255 operation: (w) .and. k w status affected: n, z encoding: 0000 1011 kkkk kkkk description: the contents of w are anded with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: andlw 05fh before instruction w=a3h after instruction w = 03h
? 2004 microchip technology inc. preliminary ds39635a-page 295 pic18f6310/6410/8310/8410 andwf and w with f syntax: andwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) .and. (f) dest status affected: n, z encoding: 0001 01da ffff ffff description: the contents of w are and?ed with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: andwf reg, 0, 0 before instruction w = 17h reg = c2h after instruction w = 02h reg = c2h bc branch if carry syntax: bc n operands: -128 n 127 operation: if carry bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bc 5 before instruction pc = address (here) after instruction if carry = 1; pc = address (here + 12) if carry = 0; pc = address (here + 2)
pic18f6310/6410/8310/8410 ds39635a-page 296 preliminary ? 2004 microchip technology inc. bcf bit clear f syntax: bcf f, b {,a} operands: 0 f 255 0 b 7 a [0,1] operation: 0 f status affected: none encoding: 1001 bbba ffff ffff description: bit ?b? in register ?f? is cleared. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: bcf flag_reg, 7, 0 before instruction flag_reg = c7h after instruction flag_reg = 47h bn branch if negative syntax: bn n operands: -128 n 127 operation: if negative bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bn jump before instruction pc = address (here) after instruction if negative = 1; pc = address (jump) if negative = 0; pc = address (here + 2)
? 2004 microchip technology inc. preliminary ds39635a-page 297 pic18f6310/6410/8310/8410 bnc branch if not carry syntax: bnc n operands: -128 n 127 operation: if carry bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnc jump before instruction pc = address (here) after instruction if carry = 0; pc = address (jump) if carry = 1; pc = address (here + 2) bnn branch if not negative syntax: bnn n operands: -128 n 127 operation: if negative bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnn jump before instruction pc = address (here) after instruction if negative = 0; pc = address (jump) if negative = 1; pc = address (here + 2)
pic18f6310/6410/8310/8410 ds39635a-page 298 preliminary ? 2004 microchip technology inc. bnov branch if not overflow syntax: bnov n operands: -128 n 127 operation: if overflow bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnov jump before instruction pc = address (here) after instruction if overflow = 0; pc = address (jump) if overflow = 1; pc = address (here + 2) bnz branch if not zero syntax: bnz n operands: -128 n 127 operation: if zero bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnz jump before instruction pc = address (here) after instruction if zero = 0; pc = address (jump) if zero = 1; pc = address (here + 2)
? 2004 microchip technology inc. preliminary ds39635a-page 299 pic18f6310/6410/8310/8410 bra unconditional branch syntax: bra n operands: -1024 n 1023 operation: (pc) + 2 + 2n pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation example: here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: bsf f, b {,a} operands: 0 f 255 0 b 7 a [0,1] operation: 1 f status affected: none encoding: 1000 bbba ffff ffff description: bit ?b? in register ?f? is set. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: bsf flag_reg, 7, 1 before instruction flag_reg = 0ah after instruction flag_reg = 8ah
pic18f6310/6410/8310/8410 ds39635a-page 300 preliminary ? 2004 microchip technology inc. btfsc bit test file, skip if clear syntax: btfsc f, b {,a} operands: 0 f 255 0 b 7 a [0,1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit ?b? in register ?f? is ? 0 ?, then the next instruction is skipped. if bit ?b? is ? 0 ?, then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here false true btfsc : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false) btfss bit test file, skip if set syntax: btfss f, b {,a} operands: 0 f 255 0 b < 7 a [0,1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit ?b? in register ?f? is ? 1 ?, then the next instruction is skipped. if bit ?b? is ? 1 ?, then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here false true btfss : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true)
? 2004 microchip technology inc. preliminary ds39635a-page 301 pic18f6310/6410/8310/8410 btg bit toggle f syntax: btg f, b {,a} operands: 0 f 255 0 b < 7 a [0,1] operation: (f ) f status affected: none encoding: 0111 bbba ffff ffff description: bit ?b? in data memory location ?f? is inverted. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: btg portc, 4, 0 before instruction: portc = 0111 0101 [75h] after instruction: portc = 0110 0101 [65h] bov branch if overflow syntax: bov n operands: -128 n 127 operation: if overflow bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bov jump before instruction pc = address (here) after instruction if overflow = 1; pc = address (jump) if overflow = 0; pc = address (here + 2)
pic18f6310/6410/8310/8410 ds39635a-page 302 preliminary ? 2004 microchip technology inc. bz branch if zero syntax: bz n operands: -128 n 127 operation: if zero bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bz jump before instruction pc = address (here) after instruction if zero = 1; pc = address (jump) if zero = 0; pc = address (here + 2) call subroutine call syntax: call k {,s} operands: 0 k 1048575 s [0,1] operation: (pc) + 4 tos, k pc<20:1>, if s = 1 (w) ws, (status) statuss, (bsr) bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2-mbyte memory range. first, return address (pc + 4) is pushed onto the return stack. if ?s? = 1 , the w, status and bsr registers are also pushed into their respective shadow registers, ws, statuss and bsrs. if ?s? = 0 , no update occurs (default). then, the 20-bit value ?k? is loaded into pc<20:1>. call is a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, push pc to stack read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example: here call there,1 before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 4) ws = w bsrs = bsr statuss= status
? 2004 microchip technology inc. preliminary ds39635a-page 303 pic18f6310/6410/8310/8410 clrf clear f syntax: clrf f {,a} operands: 0 f 255 a [0,1] operation: 000h f 1 z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: clrf flag_reg,1 before instruction flag_reg = 5ah after instruction flag_reg = 00h clrwdt clear watchdog timer syntax: clrwdt operands: none operation: 000h wdt, 000h wdt postscaler, 1 to, 1 pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the postscaler of the wdt. status bits, to and pd , are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 00h wdt postscaler = 0 to =1 pd =1
pic18f6310/6410/8310/8410 ds39635a-page 304 preliminary ? 2004 microchip technology inc. comf complement f syntax: comf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: dest status affected: n, z encoding: 0001 11da ffff ffff description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: comf reg, 0, 0 before instruction reg = 13h after instruction reg = 13h w=ech (f ) cpfseq compare f with w, skip if f = w syntax: cpfseq f {,a} operands: 0 f 255 a [0,1] operation: (f) ? (w), skip if (f) = (w) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if ?f? = w , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfseq reg, 0 nequal : equal : before instruction pc address = here w=? reg = ? after instruction if reg = w; pc = address (equal) if reg w; pc = address (nequal)
? 2004 microchip technology inc. preliminary ds39635a-page 305 pic18f6310/6410/8310/8410 cpfsgt compare f with w, skip if f > w syntax: cpfsgt f {,a} operands: 0 f 255 a [0,1] operation: (f) ? ( w), skip if (f) > (w) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location ?f? to the contents of the w by performing an unsigned subtraction. if the contents of ?f? are greater than the contents of wre g, then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfsgt reg, 0 ngreater : greater : before instruction pc = address (here) w= ? after instruction if reg > w; pc = address (greater) if reg w; pc = address (ngreater) cpfslt compare f with w, skip if f < w syntax: cpfslt f {,a} operands: 0 f 255 a [0,1] operation: (f) ? ( w), skip if (f) < (w) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if the contents of ?f? are less than the contents of w, then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfslt reg, 1 nless : less : before instruction pc = address (here) w= ? after instruction if reg < w; pc = address (less) if reg w; pc = address (nless)
pic18f6310/6410/8310/8410 ds39635a-page 306 preliminary ? 2004 microchip technology inc. daw decimal adjust w register syntax: daw operands: none operation: if [w<3:0> >9] or [dc = 1 ] then (w<3:0>) + 6 w<3:0>; else ( w<3:0>) w<3:0>; if [w<7:4> > 9] or [c = 1 ] then ( w<7:4>) + 6 w<7:4> c = 1 ; else (w<7:4>) w<7:4>; status affected: c encoding: 0000 0000 0000 0111 description: daw adjusts the eight-bit value in w, resulting from the earlier addition of two variables (each in packed bcd format) and produces a correct packed bcd result. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register w process data write w example 1: daw before instruction w=a5h c=0 dc = 0 after instruction w = 05h c=1 dc = 0 example 2: before instruction w=ceh c=0 dc = 0 after instruction w = 34h c=1 dc = 0 decf decrement f syntax: decf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest status affected: c, dc, n, ov, z encoding: 0000 01da ffff ffff description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: decf cnt, 1, 0 before instruction cnt = 01h z=0 after instruction cnt = 00h z=1
? 2004 microchip technology inc. preliminary ds39635a-page 307 pic18f6310/6410/8310/8410 decfsz decrement f, skip if 0 syntax: decfsz f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is ? 0 ?, the next instruction, which is already fetched, is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here decfsz cnt, 1, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt ? 1 if cnt = 0; pc = address (continue) if cnt 0; pc = address (here + 2) dcfsnz decrement f, skip if not 0 syntax: dcfsnz f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is not ? 0 ?, the next instruction, which is already fetched, is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is 1 , the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here dcfsnz temp, 1, 0 zero : nzero : before instruction temp = ? after instruction temp = temp ? 1, if temp = 0; pc = address (zero) if temp 0; pc = address (nzero)
pic18f6310/6410/8310/8410 ds39635a-page 308 preliminary ? 2004 microchip technology inc. goto unconditional branch syntax: goto k operands: 0 k 1048575 operation: k pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within entire 2-mbyte memory range. the 20-bit value ?k? is loaded into pc<20:1>. goto is always a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, no operation read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example: goto there after instruction pc = address (there) incf increment f syntax: incf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest status affected: c, dc, n, ov, z encoding: 0010 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: incf cnt, 1, 0 before instruction cnt = ffh z=0 c=? dc = ? after instruction cnt = 00h z=1 c=1 dc = 1
? 2004 microchip technology inc. preliminary ds39635a-page 309 pic18f6310/6410/8310/8410 incfsz increment f, skip if 0 syntax: incfsz f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f?. (default) if the result is ? 0 ?, the next instruction, which is already fetched, is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here incfsz cnt, 1, 0 nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address (zero) if cnt 0; pc = address (nzero) infsnz increment f, skip if not 0 syntax: infsnz f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is not ? 0 ?, the next instruction, which is already fetched, is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here infsnz reg, 1, 0 zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg 0; pc = address (nzero) if reg = 0; pc = address (zero)
pic18f6310/6410/8310/8410 ds39635a-page 310 preliminary ? 2004 microchip technology inc. iorlw inclusive or literal with w syntax: iorlw k operands: 0 k 255 operation: (w) .or. k w status affected: n, z encoding: 0000 1001 kkkk kkkk description: the contents of w are ored with the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: iorlw 35h before instruction w=9ah after instruction w=bfh iorwf inclusive or w with f syntax: iorwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) .or. (f) dest status affected: n, z encoding: 0001 00da ffff ffff description: inclusive or w with register ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: iorwf result, 0, 1 before instruction result = 13h w = 91h after instruction result = 13h w = 93h
? 2004 microchip technology inc. preliminary ds39635a-page 311 pic18f6310/6410/8310/8410 lfsr load fsr syntax: lfsr f, k operands: 0 f 2 0 k 4095 operation: k fsrf status affected: none encoding: 1110 1111 1110 0000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal ?k? is loaded into the file select register pointed to by ?f?. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? msb process data write literal ?k? msb to fsrfh decode read literal ?k? lsb process data write literal ?k? to fsrfl example: lfsr 2, 3abh after instruction fsr2h = 03h fsr2l = abh movf move f syntax: movf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: f dest status affected: n, z encoding: 0101 00da ffff ffff description: the contents of register ?f? are moved to a destination dependent upon the status of ?d?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write w example: movf reg, 0, 0 before instruction reg = 22h w=ffh after instruction reg = 22h w = 22h
pic18f6310/6410/8310/8410 ds39635a-page 312 preliminary ? 2004 microchip technology inc. movff move f to f syntax: movff f s ,f d operands: 0 f s 4095 0 f d 4095 operation: (f s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff fff f s fff f d description: the contents of source register ?f s ? are moved to destination register ?f d ?. location of source ?f s ? can be anywhere in the 4096-byte data space (000h to fffh) and location of destination ?f d ? can also be anywhere from 000h to fffh. either source or destination can be w (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register words: 2 cycles: 2 (3) q cycle activity: q1 q2 q3 q4 decode read register ?f? (src) process data no operation decode no operation no dummy read no operation write register ?f? (dest) example: movff reg1, reg2 before instruction reg1 = 33h reg2 = 11h after instruction reg1 = 33h reg2 = 33h movlb move literal to low nibble in bsr syntax: movlw k operands: 0 k 255 operation: k bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the eight-bit literal ?k? is loaded into the bank select register (bsr). the value of bsr<7:4> always remains ? 0 ?, regardless of the value of k 7 :k 4 . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write literal ?k? to bsr example: movlb 5 before instruction bsr register = 02h after instruction bsr register = 05h
? 2004 microchip technology inc. preliminary ds39635a-page 313 pic18f6310/6410/8310/8410 movlw move literal to w syntax: movlw k operands: 0 k 255 operation: k w status affected: none encoding: 0000 1110 kkkk kkkk description: the eight-bit literal ?k? is loaded into w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: movlw 5ah after instruction w=5ah movwf move w to f syntax: movwf f {,a} operands: 0 f 255 a [0,1] operation: (w) f status affected: none encoding: 0110 111a ffff ffff description: move data from w to register ?f?. location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: movwf reg, 0 before instruction w=4fh reg = ffh after instruction w=4fh reg = 4fh
pic18f6310/6410/8310/8410 ds39635a-page 314 preliminary ? 2004 microchip technology inc. mullw multiply literal with w syntax: mullw k operands: 0 k 255 operation: (w) x k prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is carried out between the contents of w and the 8-bit literal ?k?. the 16-bit result is placed in prodh:prodl register pair. prodh contains the high byte. w is unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write registers prodh: prodl example: mullw 0c4h before instruction w=e2h prodh = ? prodl = ? after instruction w=e2h prodh = adh prodl = 08h mulwf multiply w with f syntax: mulwf f {,a} operands: 0 f 255 a [0,1] operation: (w) x (f) prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is carried out between the contents of w and the register file location ?f?. the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both w and ?f? are unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write registers prodh: prodl example: mulwf reg, 1 before instruction w=c4h reg = b5h prodh = ? prodl = ? after instruction w=c4h reg = b5h prodh = 8ah prodl = 94h
? 2004 microchip technology inc. preliminary ds39635a-page 315 pic18f6310/6410/8310/8410 negf negate f syntax: negf f {,a} operands: 0 f 255 a [0,1] operation: ( f ) + 1 f status affected: n, ov, c, dc, z encoding: 0110 110a ffff ffff description: location ?f? is negated using two?s complement. the result is placed in the data memory location ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : negf reg, 1 before instruction reg = 0011 1010 [3ah] after instruction reg = 1100 0110 [c6h] nop no operation syntax: nop operands: none operation: no operation status affected: none encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example: none.
pic18f6310/6410/8310/8410 ds39635a-page 316 preliminary ? 2004 microchip technology inc. pop pop top of return stack syntax: pop operands: none operation: (tos) bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example: pop goto new before instruction tos = 0031a2h stack (1 level down) = 014332h after instruction tos = 014332h pc = new push push top of return stack syntax: push operands: none operation: (pc + 2) tos status affected: none encoding: 0000 0000 0000 0101 description: the pc + 2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows implementing a software stack by modifying tos and then pushing it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc + 2 onto return stack no operation no operation example: push before instruction tos = 345ah pc = 0124h after instruction pc = 0126h tos = 0126h stack (1 level down) = 345ah
? 2004 microchip technology inc. preliminary ds39635a-page 317 pic18f6310/6410/8310/8410 rcall relative call syntax: rcall n operands: -1024 n 1023 operation: (pc) + 2 tos, (pc) + 2 + 2n pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc + 2) is pushed onto the stack. then, add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? push pc to stack process data write to pc no operation no operation no operation no operation example: here rcall jump before instruction pc = address (here) after instruction pc = address (jump) tos = address (here + 2) reset reset syntax: reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset in software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example: reset after instruction registers = reset value flags* = reset value
pic18f6310/6410/8310/8410 ds39635a-page 318 preliminary ? 2004 microchip technology inc. retfie return from interrupt syntax: retfie {s} operands: s [0,1] operation: (tos) pc, 1 gie/gieh or peie/giel, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged. status affected: gie/gieh, peie/giel. encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting either the high or low priority global interrupt enable bit. if ?s? = 1 , the contents of the shadow registers, ws, statuss and bsrs, are loaded into their corresponding registers, w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example: retfie 1 after interrupt pc = tos w=ws bsr = bsrs status = statuss gie/gieh, peie/giel = 1 retlw return literal to w syntax: retlw k operands: 0 k 255 operation: k w, (tos) pc, pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: w is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data pop pc from stack, write to w no operation no operation no operation no operation example: call table ; w contains table ; offset value ; w now has ; table value : table addwf pcl ; w = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction w = 07h after instruction w = value of kn
? 2004 microchip technology inc. preliminary ds39635a-page 319 pic18f6310/6410/8310/8410 return return from subroutine syntax: return {s} operands: s [0,1] operation: (tos) pc, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. if ?s?= 1 , the contents of the shadow registers, ws, statuss and bsrs, are loaded into their corresponding registers, w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example: return after instruction: pc = tos rlcf rotate left f through carry syntax: rlcf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<7>) c, (c) dest<0> status affected: c, n, z encoding: 0011 01da ffff ffff description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: rlcf reg, 0, 0 before instruction reg = 1110 0110 c=0 after instruction reg = 1110 0110 w= 1100 1100 c=1 c register f
pic18f6310/6410/8310/8410 ds39635a-page 320 preliminary ? 2004 microchip technology inc. rlncf rotate left f (no carry) syntax: rlncf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<7>) dest<0> status affected: n, z encoding: 0100 01da ffff ffff description: the contents of register ?f? are rotated one bit to the left. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: rlncf reg, 1, 0 before instruction reg = 1010 1011 after instruction reg = 0101 0111 register f rrcf rotate right f through carry syntax: rrcf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<0>) c, (c) dest<7> status affected: c, n, z encoding: 0011 00da ffff ffff description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: rrcf reg, 0, 0 before instruction reg = 1110 0110 c=0 after instruction reg = 1110 0110 w= 0111 0011 c=0 c register f
? 2004 microchip technology inc. preliminary ds39635a-page 321 pic18f6310/6410/8310/8410 rrncf rotate right f (no carry) syntax: rrncf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<0>) dest<7> status affected: n, z encoding: 0100 00da ffff ffff description: the contents of register ?f? are rotated one bit to the right. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: rrncf reg, 1, 0 before instruction reg = 1101 0111 after instruction reg = 1110 1011 example 2: rrncf reg, 0, 0 before instruction w=? reg = 1101 0111 after instruction w= 1110 1011 reg = 1101 0111 register f setf set f syntax: setf f {,a} operands: 0 f 255 a [0,1] operation: ffh f status affected: none encoding: 0110 100a ffff ffff description: the contents of the specified register are set to ffh. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: setf reg,1 before instruction reg = 5ah after instruction reg = ffh
pic18f6310/6410/8310/8410 ds39635a-page 322 preliminary ? 2004 microchip technology inc. sleep enter sleep mode syntax: sleep operands: none operation: 00h wdt, 0 wdt postscaler, 1 to , 0 pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example : sleep before instruction to =? pd =? after instruction to =1 ? pd =0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from w with borrow syntax: subfwb f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) ? (f) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register ?f? and carry flag (borrow) from w (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in index ed litera l offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1 : subfwb reg, 1, 0 before instruction reg = 3 w=2 c=1 after instruction reg = ff w=2 c=0 z=0 n = 1 ; result is negative example 2: subfwb reg, 0, 0 before instruction reg = 2 w=5 c=1 after instruction reg = 2 w=3 c=1 z=0 n = 0 ; result is positive example 3: subfwb reg, 1, 0 before instruction reg = 1 w=2 c=0 after instruction reg = 0 w=2 c=1 z = 1 ; result is zero n=0
? 2004 microchip technology inc. preliminary ds39635a-page 323 pic18f6310/6410/8310/8410 sublw subtract w from literal syntax: sublw k operands: 0 k 255 operation: k ? (w) w status affected: n, ov, c, dc, z encoding: 0000 1000 kkkk kkkk description: w is subtracted from the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example 1: sublw 02h before instruction w = 01h c=? after instruction w = 01h c = 1 ; result is positive z=0 n=0 example 2: sublw 02h before instruction w = 02h c=? after instruction w = 00h c = 1 ; result is zero z=1 n=0 example 3: sublw 02h before instruction w = 03h c=? after instruction w = ffh ; (2?s complement) c = 0 ; result is negative z=0 n=1 subwf subtract w from f syntax: subwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (w) dest status affected: n, ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract w from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is v, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is v, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in index ed litera l offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subwf reg, 1, 0 before instruction reg = 3 w=2 c=? after instruction reg = 1 w=2 c = 1 ; result is positive z=0 n=0 example 2: subwf reg, 0, 0 before instruction reg = 2 w=2 c=? after instruction reg = 2 w=0 c = 1 ; result is zero z=1 n=0 example 3: subwf reg, 1, 0 before instruction reg = 1 w=2 c=? after instruction reg = ffh ;(2?s complement) w=2 c = 0 ; result is negative z=0 n=1
pic18f6310/6410/8310/8410 ds39635a-page 324 preliminary ? 2004 microchip technology inc. subwfb subtract w from f with borrow syntax: subwfb f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (w) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract w and the carry flag (borrow) from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed litera l offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subwfb reg, 1, 0 before instruction reg = 19h (0001 1001) w=0dh (0000 1101) c=1 after instruction reg = 0ch (0000 1011) w=0dh (0000 1101) c=1 z=0 n = 0 ; result is positive example 2: subwfb reg, 0, 0 before instruction reg = 1bh (0001 1011) w =1ah (0001 1010) c=0 after instruction reg = 1bh (0001 1011) w = 00h c=1 z = 1 ; result is zero n=0 example 3: subwfb reg, 1, 0 before instruction reg = 03h (0000 0011) w=0eh (0000 1101) c=1 after instruction reg = f5h (1111 0100) ; [2?s comp] w=0eh (0000 1101) c=0 z=0 n = 1 ; result is negative swapf swap f syntax: swapf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: swapf reg, 1, 0 before instruction reg = 53h after instruction reg = 35h
? 2004 microchip technology inc. preliminary ds39635a-page 325 pic18f6310/6410/8310/8410 tblrd table read syntax: tblrd ( *; *+; *-; +*) operands: none operation: if tblrd *, (prog mem (tblptr)) tablat; tblptr ? no change; if tblrd *+, (prog mem (tblptr)) tablat; (tblptr) + 1 tblptr; if tblrd *-, (prog mem (tblptr)) tablat; (tblptr) ? 1 tblptr; if tblrd +*, (tblptr) + 1 tblptr; (prog mem (tblptr)) tablat; status affected: none encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to read the contents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 : most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tablat) tblrd table read (continued) example 1: tblrd *+ ; before instruction tablat = 55h tblptr = 00a356h memory(00a356h) = 34h after instruction tablat = 34h tblptr = 00a357h example 2: tblrd +* ; before instruction tablat = aah tblptr = 01a357h memory(01a357h) = 12h memory(01a358h) = 34h after instruction tablat = 34h tblptr = 01a358h
pic18f6310/6410/8310/8410 ds39635a-page 326 preliminary ? 2004 microchip technology inc. tblwt table write syntax: tblwt ( *; *+; *-; +*) operands: none operation: if tblwt*, (tablat) holding register; tblptr ? no change; if tblwt*+, (tablat) holding register; (tblptr) + 1 tblptr; if tblwt*-, (tablat) holding register; (tblptr) ? 1 tblptr; if tblwt+*, (tblptr) + 1 tblptr; (tablat) holding register; status affected: none encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction uses the 3 lsbs of tblptr to determine which of the 8 holding registers the tablat is written to. the holding registers are used to program the contents of program memory (p.m.). (refer to section 6.0 ?program memory? for additional details on programming flash memory.) the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 : most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register ) tblwt table write (continued) example 1: tblwt *+; before instruction tablat = 55h tblptr = 00a356h holding register (00a356h) = ffh after instructions (table write completion) tablat = 55h tblptr = 00a357h holding register (00a356h) = 55h example 2: tblwt +*; before instruction tablat = 34h tblptr = 01389ah holding register (01389ah) = ffh holding register (01389bh) = ffh after instruction (table write completion) tablat = 34h tblptr = 01389bh holding register (01389ah) = ffh holding register (01389bh) = 34h note: the tblwt instruction is not available in pic18f6310/6410 devices (i.e., 64-pin devices) in normal operating modes. tblwt can only be used by pic18f8310/8410 devices with the external memory interface and only when writing to an external memory device. for more information, refer to section 6.4 ?writing to program memory space (pic18f8310/8410 only)? and section 6.6 ?writing and erasing on-chip program memory (icsp mode)? .
? 2004 microchip technology inc. preliminary ds39635a-page 327 pic18f6310/6410/8310/8410 tstfsz test f, skip if 0 syntax: tstfsz f {,a} operands: 0 f 255 a [0,1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if ?f? = 0 , the next instruction, fetched during the current instruction execution, is discarded and a nop is executed, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here tstfsz cnt, 1 nzero : zero : before instruction pc = address (here) after instruction if cnt = 00h, pc = address (zero) if cnt 00h, pc = address (nzero) xorlw exclusive or literal with w syntax: xorlw k operands: 0 k 255 operation: (w) .xor. k w status affected: n, z encoding: 0000 1010 kkkk kkkk description: the contents of w are xored with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: xorlw 0afh before instruction w=b5h after instruction w=1ah
pic18f6310/6410/8310/8410 ds39635a-page 328 preliminary ? 2004 microchip technology inc. xorwf exclusive or w with f syntax: xorwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) .xor. (f) dest status affected: n, z encoding: 0001 10da ffff ffff description: exclusive or the contents of w with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in the register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 24.2.3 for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : xorwf reg, 1, 0 before instruction reg = afh w=b5h after instruction reg = 1ah w=b5h
? 2004 microchip technology inc. preliminary ds39635a-page 329 pic18f6310/6410/8310/8410 24.2 extended instruction set in addition to the standard 75 instructions of the pic18 instruction set, pic18fx310/x410 devices also provide an optional extension to the core cpu function- ality. the added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of indexed literal offset addressing for many of the standard pic18 instructions. the additional features of the extended instruction set are disabled by default. to enable them, users must set the xinst configuration bit. the instructions in the extended set can all be classi- fied as literal operations which either manipulate the file select registers, or use them for indexed address- ing. two of the instructions, addfsr and subfsr , each have an additional special instantiation for using fsr2. these versions ( addulnk and subulnk ) allow for automatic return after execution. the extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly c. among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. these include: dynamic allocation and de-allocation of software stack space when entering and leaving subroutines function pointer invocation software stack pointer manipulation manipulation of variables located in a software stack a summary of the instructions in the extended instruc- tion set is provided in table 24-3. detailed descriptions are provided in section 24.2.2 ?extended instruction set? . the opcode field descriptions in table 24-1 (page 288) apply to both the standard and extended pic18 instruction sets. 24.2.1 extended instruction syntax most of the extended instructions use indexed argu- ments, using one of the file select registers and some offset to specify a source or destination register. when an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets (?[ ]?). this is done to indicate that the argument is used as an index or offset. the mpasm assembler will flag an error if it determines that an index or offset value is not bracketed. when the extended instruction set is enabled, brackets are also used to indicate index arguments in byte-oriented and bit-oriented instructions. this is in addition to other changes in their syntax. for more details, see section 24.2.3.1 ?extended instruction syntax with standard pic18 commands? . table 24-3: extensions to the pic18 instruction set note: the instruction set extension and the indexed literal offset addressing mode were designed for optimizing applications written in c; the user may likely never use these instructions directly in assembler. the syntax for these commands is pro- vided as a reference for users who may be reviewing code that has been generated by a compiler. note: in the past, square brackets have been used to denote optional arguments in the pic18 and earlier instruction sets. in this text and going forward, optional arguments are denoted by braces (?{ }?). mnemonic, operands description cycles 16-bit instruction word status affected msb lsb addfsr addulnk callw movsf movss pushl subfsr subulnk f, k k z s , f d z s , z d k f, k k add literal to fsr add literal to fsr2 and return call subroutine using wreg move z s (source) to 1st word f d (destination) 2nd word move z s (source) to 1st word z d (destination) 2nd word store literal at fsr2, decrement fsr2 subtract literal from fsr subtract literal from fsr2 and return 1 2 2 2 2 1 1 2 1110 1110 0000 1110 1111 1110 1111 1110 1110 1110 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk ffkk 11kk kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk none none none none none none none none note: all pic18 instructions may take an optional label argument, preceding the instruction mnemonic, for use in symbolic addressing. if a label is used, the instruction syntax then becomes: {label} instruction argument(s)
pic18f6310/6410/8310/8410 ds39635a-page 330 preliminary ? 2004 microchip technology inc. 24.2.2 extended instruction set addfsr add literal to fsr syntax: addfsr f, k operands: 0 k 63 f [0, 1, 2] operation: fsr(f) + k fsr(f) status affected: none encoding: 1110 1000 ffkk kkkk description: the 6-bit literal ?k? is added to the contents of the fsr specified by ?f?. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to fsr example: addfsr 2, 23h before instruction fsr2 = 03ffh after instruction fsr2 = 0422h addulnk add literal to fsr2 and return syntax: addulnk k operands: 0 k 63 operation: fsr2 + k fsr2, (tos) pc status affected: none encoding: 1110 1000 11kk kkkk description: the 6-bit literal ?k? is added to the contents of fsr2. a return is then executed by loading the pc with the tos. the instruction takes two cycles to execute; a nop is performed during the second cycle. this may be though of as a special case of the addfsr instruction, where f = 3 (binary ? 11 ?); it operates only on fsr2. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to fsr no operation no operation no operation no operation example: addulnk 23h before instruction fsr2 = 03ffh pc = 0100h after instruction fsr2 = 0422h pc = (tos)
? 2004 microchip technology inc. preliminary ds39635a-page 331 pic18f6310/6410/8310/8410 callw subroutine call using wreg syntax: callw operands: none operation: (pc + 2) tos, (w) pcl, (pclath) pch, (pclatu) pcu status affected: none encoding: 0000 0000 0001 0100 description first, the return address (pc + 2) is pushed onto the return stack. next, the contents of w are written to pcl; the existing value is discarded. then, the contents of pclath and pclatu are latched into pch and pcu, respectively. the second cycle is executed as a nop instruction while the new next instruction is fetched. unlike call , there is no option to update w, status or bsr. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read wreg push pc to stack no operation no operation no operation no operation no operation example : here callw before instruction pc = address (here) pclath = 10h pclatu = 00h w = 06h after instruction pc = 001006h tos = address (here + 2) pclath = 10h pclatu = 00h w = 06h movsf move indexed to f syntax: movsf [z s ], f d operands: 0 z s 127 0 f d 4095 operation: ((fsr2) + z s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1110 1111 1011 ffff 0zzz ffff zzzz s ffff d description: the contents of the source register are moved to destination register ?f d ?. the actual address of the source register is determined by adding the 7-bit literal offset ?z s ? in the first word to the value of fsr2. the address of the destination register is specified by the 12-bit literal ?f d ? in the second word. both addresses can be anywhere in the 4096-byte data space (000h to fffh). the movsf instruction cannot use the pcl, tosu, tosh or tosl as the destination register. if the resultant source address points to an indirect addressing register, the value returned will be 00h. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode determine source addr determine source addr read source reg decode no operation no dummy read no operation write register ?f? (dest) example : movsf [05h], reg2 before instruction fsr2 = 80h contents of 85h = 33h reg2 = 11h after instruction fsr2 = 80h contents of 85h = 33h reg2 = 33h
pic18f6310/6410/8310/8410 ds39635a-page 332 preliminary ? 2004 microchip technology inc. movss move indexed to indexed syntax: movss [z s ], [z d ] operands: 0 z s 127 0 z d 127 operation: ((fsr2) + z s ) ((fsr2) + z d ) status affected: none encoding: 1st word (source) 2nd word (dest.) 1110 1111 1011 xxxx 1zzz xzzz zzzz s zzzz d description the contents of the source register are moved to the destination register. the addresses of the source and destination registers are determined by adding the 7-bit literal offsets ?z s ? or ?z d ?, respectively, to the value of fsr2. both registers can be located anywhere in the 4096-byte data memory space (000h to fffh). the movss instruction cannot use the pcl, tosu, tosh or tosl as the destination register. if the resultant source address points to an indirect addressing register, the value returned will be 00h. if the resultant destination address points to an indirect addressing register, the instruction will execute as a nop . words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode determine source addr determine source addr read source reg decode determine dest addr determine dest addr write to dest reg example : movss [05h], [06h] before instruction fsr2 = 80h contents of 85h = 33h contents of 86h = 11h after instruction fsr2 = 80h contents of 85h = 33h contents of 86h = 33h pushl store literal at fsr2, decrement fsr2 syntax: pushl k operands: 0 k 255 operation: k (fsr2), fsr2 - 1 fsr2 status affected: none encoding: 1111 1010 kkkk kkkk description: the 8-bit literal ?k? is written to the data memory address specified by fsr2. fsr2 is decremented by ? 1 ? after the operation. this instruction allows users to push values onto a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write to destination example : pushl 08h before instruction fsr2h:fsr2l = 01ech memory (01ech) = 00h after instruction fsr2h:fsr2l = 01ebh memory (01ech) = 08h
? 2004 microchip technology inc. preliminary ds39635a-page 333 pic18f6310/6410/8310/8410 subfsr subtract literal from fsr syntax: subfsr f, k operands: 0 k 63 f [ 0, 1, 2 ] operation: fsrf ? k fsrf status affected: none encoding: 1110 1001 ffkk kkkk description: the 6-bit literal ?k? is subtracted from the contents of the fsr specified by ?f?. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: subfsr 2, 23h before instruction fsr2 = 03ffh after instruction fsr2 = 03dch subulnk subtract literal from fsr2 and return syntax: subulnk k operands: 0 k 63 operation: fsr2 ? k fsr2 (tos) pc status affected: none encoding: 1110 1001 11kk kkkk description: the 6-bit literal ?k? is subtracted from the contents of the fsr2. a return is then executed by loading the pc with the tos. the instruction takes two cycles to execute; a nop is performed during the second cycle. this may be though of as a special case of the subfsr instruction, where f = 3 (binary ? 11 ?); it operates only on fsr2. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination no operation no operation no operation no operation example: subulnk 23h before instruction fsr2 = 03ffh pc = 0100h after instruction fsr2 = 03dch pc = (tos)
pic18f6310/6410/8310/8410 ds39635a-page 334 preliminary ? 2004 microchip technology inc. 24.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode in addition to eight new commands in the extended set, enabling the extended instruction set also enables indexed literal offset addressing ( section 5.6.1 ?indexed addressing with literal offset? ). this has a significant impact on the way that many commands of the standard pic18 instruction set are interpreted. when the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the access bank (a = 0 ) or in a gpr bank designated by the bsr (a = 1 ). when the extended instruction set is enabled and a = 0 , however, a file register argument of 5fh or less is interpreted as an offset from the pointer value in fsr2 and not as a literal address. for practical purposes, this means that all instructions that use the access ram bit as an argument ? that is, all byte-oriented and bit-oriented instructions, or almost half of the core pic18 instructions ? may behave differently when the extended instruction set is enabled. when the content of fsr2 is 00h, the boundaries of the access ram are essentially remapped to their original values. this may be useful in creating backward compatible code. if this technique is used, it may be necessary to save the value of fsr2 and restore it when moving back and forth between c and assembly routines in order to preserve the stack pointer. users must also keep in mind the syntax requirements of the extended instruction set (see section 24.2.3.1 ?extended instruction syntax with standard pic18 commands? ). although the indexed literal offset mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. users who are accustomed to the pic18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5fh or less are used for indexed literal offset addressing. representative examples of typical byte-oriented and bit-oriented instructions in the indexed literal offset mode are provided on the following page to show how execution is affected. the operand conditions shown in the examples are applicable to all instructions of these types. 24.2.3.1 extended instruction syntax with standard pic18 commands when the extended instruction set is enabled, the file register argument ?f? in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value ?k?. as already noted, this occurs only when f is less than or equal to 5fh. when an offset value is used, it must be indicated by square brackets (?[ ]?). as with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. omitting the brackets, or using a value greater than 5fh within brackets, will generate an error in the mpasm assembler. if the index argument is properly bracketed for indexed literal offset addressing, the access ram argument is never specified; it will automatically be assumed to be ? 0 ?. this is in contrast to standard operation (extended instruction set disabled), when ?a? is set on the basis of the target address. declaring the access ram bit in this mode will also generate an error in the mpasm assembler. the destination argument ?d? functions as before. in the latest versions of the mpasm assembler, language support for the extended instruction set must be explicitly invoked. this is done with either the command line option /y , or the pe directive in the source listing. 24.2.4 considerations when enabling the extended instruction set it is important to note that the extensions to the instruc- tion set may not be beneficial to all users. in particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. additionally, the indexed literal offset addressing mode may create issues with legacy applications writ- ten to pic18 assembler. this is because instructions in the legacy code may attempt to address registers in the access bank below 5fh. since these addresses are interpreted as literal offsets to fsr2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. when porting an application to the pic18fx310/x410, it is very important to consider the type of code. a large, re-entrant application that is written in c and would benefit from efficient compilation will do well when using the instruction set extensions. legacy applica- tions that heavily use the access bank will most likely not benefit from using the extended instruction set. note: enabling the pic18 instruction set exten- sion may cause legacy applications to behave erratically or fail entirely.
? 2004 microchip technology inc. preliminary ds39635a-page 335 pic18f6310/6410/8310/8410 addwf add w to indexed (indexed literal offset mode) syntax: addwf [k] {,d} operands: 0 k 95 d [0,1] operation: (w) + ((fsr2) + k) dest status affected: n, ov, c, dc, z encoding: 0010 01d0 kkkk kkkk description: the contents of w are added to the contents of the register indicated by fsr2, offset by the value ?k?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write to destination example : addwf [ofst] ,0 before instruction w = 17h ofst = 2ch fsr2 = 0a00h contents of 0a2ch = 20h after instruction w = 37h contents of 0a2ch = 20h bsf bit set indexed (indexed literal offset mode) syntax: bsf [k], b operands: 0 f 95 0 b 7 operation: 1 ((fsr2) + k) status affected: none encoding: 1000 bbb0 kkkk kkkk description: bit ?b? of the register indicated by fsr2, offset by the value ?k?, is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : bsf [flag_ofst], 7 before instruction flag_ofst = 0ah fsr2 = 0a00h contents of 0a0ah = 55h after instruction contents of 0a0ah = d5h setf set indexed (indexed literal offset mode) syntax: setf [k] operands: 0 k 95 operation: ffh ((fsr2) + k) status affected: none encoding: 0110 1000 kkkk kkkk description: the contents of the register indicated by fsr2, offset by ?k?, are set to ffh. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write register example : setf [ofst] before instruction ofst = 2ch fsr2 = 0a00h contents of 0a2ch = 00h after instruction contents of 0a2ch = ffh
pic18f6310/6410/8310/8410 ds39635a-page 336 preliminary ? 2004 microchip technology inc. 24.2.5 special considerations with microchip mplab ide tools the latest versions of microchip?s software tools have been designed to fully support the extended instruction set of the pic18fx310/x410 family of devices. this includes the mplab c18 compiler, mpasm assembly language and mplab integrated development environment (ide). when selecting a target device for software develop- ment, mplab ide will automatically set default config- uration bits for that device. the default setting for the xinst configuration is ? 0 ?, disabling the extended instruction set and indexed literal offset addressing. for proper execution of applications developed to take advantage of the extended instruction set, xinst must be set during programming. to develop software for the extended instruction set, the user must enable support for the instructions and the indexed addressing mode in their language tool(s). depending on the environment being used, this may be done in several ways: a menu option or dialog box within the environment that allows the user to configure the language tool and its settings for the project a command line option a directive in the source code these options vary between different compilers, assemblers and development environments. users are encouraged to review the documentation accompanying their development systems for the appropriate information.
? 2004 microchip technology inc. preliminary ds39635a-page 337 pic18fx310/x410 25.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian - mplab c30 c compiler - mplab asm30 assembler/linker/library simulators - mplab sim software simulator - mplab dspic30 software simulator emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator in-circuit debugger - mplab icd 2 device programmers -pro mate ? ii universal device programmer - picstart ? plus development programmer - mplab pm3 device programmer low-cost demonstration boards - picdem tm 1 demonstration board - picdem.net tm demonstration board - picdem 2 plus demonstration board - picdem 3 demonstration board - picdem 4 demonstration board - picdem 17 demonstration board - picdem 18r demonstration board - picdem lin demonstration board - picdem usb demonstration board evaluation kits -k ee l oq ? evaluation and programming tools - picdem msc -microid ? developer kits -can - powersmart ? developer kits -analog 25.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor with color coded context a multiple project manager customizable data windows with direct edit of contents high-level source code debugging mouse over variable inspection extensive on-line help the mplab ide allows you to: edit your source files (either assembly or c) one touch assemble (or compile) and download to picmicro emulator and simulator tools (automatically updates all project information) debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increasing flexibility and power. 25.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol ref- erence, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: integration into mplab ide projects user defined macros to streamline assembly code conditional assembly for multi-purpose source files directives that allow complete control over the assembly process
pic18fx310/x410 ds39635a-page 338 preliminary ? 2004 microchip technology inc. 25.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 25.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 25.5 mplab c30 c compiler the mplab c30 c compiler is a full-featured, ansi compliant, optimizing compiler that translates standard ansi c programs into dspic30f assembly language source. the compiler also supports many command line options and language extensions to take full advantage of the dspic30f device hardware capabili- ties and afford fine control of the compiler code generator. mplab c30 is distributed with a complete ansi c standard library. all library functions have been vali- dated and conform to the ansi c library standard. the library includes functions for string manipulation, dynamic memory allocation, data conversion, time- keeping and math functions (trigonometric, exponential and hyperbolic). the compiler provides symbolic information for high-level source debugging with the mplab ide. 25.6 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 compiler uses the assembler to produce it?s object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire dspic30f instruction set support for fixed-point and floating-point data command line interface rich directive set flexible macro language mplab ide compatibility 25.7 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. the execu- tion can be performed in single-step, execute until break or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and mplab c18 c compilers, as well as the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 25.8 mplab sim30 software simulator the mplab sim30 software simulator allows code development in a pc hosted environment by simulating the dspic30f series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. the mplab sim30 simulator fully supports symbolic debugging using the mplab c30 c compiler and mplab asm30 assembler. the simulator runs in either a command line mode for automated tasks, or from mplab ide. this high-speed simulator is designed to debug, analyze and optimize time intensive dsp routines.
? 2004 microchip technology inc. preliminary ds39635a-page 339 pic18fx310/x410 25.9 mplab ice 2000 high-performance universal in-circuit emulator the mplab ice 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 25.10 mplab ice 4000 high-performance universal in-circuit emulator the mplab ice 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high- end picmicro microcontrollers. software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab icd 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high-speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, up to 2 mb of emulation memory and the ability to view variables in real-time. the mplab ice 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 25.11 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro microcontrollers. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, cpu status and peripheral registers. running at full speed enables testing hardware and applications in real-time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 25.12 pro mate ii universal device programmer the pro mate ii is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features an lcd display for instructions and error messages and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. 25.13 mplab pm3 device programmer the mplab pm3 is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modular detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand- alone mode, the mplab pm3 device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. mplab pm3 connects to the host pc via an rs- 232 or usb cable. mplab pm3 has high-speed com- munications and optimized algorithms for quick pro- gramming of large memory devices and incorporates an sd/mmc card for file storage and secure data appli- cations.
pic18fx310/x410 ds39635a-page 340 preliminary ? 2004 microchip technology inc. 25.14 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most picmicro devices up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 25.15 picdem 1 picmicro demonstration board the picdem 1 demonstration board demonstrates the capabilities of the pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the sample microcontrollers provided with the picdem 1 demonstration board can be programmed with a pro mate ii device program- mer or a picstart plus development programmer. the picdem 1 demonstration board can be connected to the mplab ice in-circuit emulator for testing. a prototype area extends the circuitry for additional appli- cation components. features include an rs-232 interface, a potentiometer for simulated analog input, push button switches and eight leds. 25.16 picdem.net internet/ethernet demonstration board the picdem.net demonstration board is an internet/ ethernet demonstration board using the pic18f452 microcontroller and tcp/ip firmware. the board supports any 40-pin dip device that conforms to the standard pinout used by the pic16f877 or pic18c452. this kit features a user friendly tcp/ip stack, web server with html, a 24l256 serial eeprom for xmodem download to web pages into serial eeprom, icsp/mplab icd 2 interface con- nector, an ethernet interface, rs-232 interface and a 16 x 2 lcd display. also included is the book and cd-rom ?tcp/ip lean, web servers for embedded systems,? by jeremy bentham 25.17 picdem 2 plus demonstration board the picdem 2 plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including pic16f87x and pic18fxx2 devices. all the neces- sary hardware and software is included to run the dem- onstration programs. the sample microcontrollers provided with the picdem 2 demonstration board can be programmed with a pro mate ii device program- mer, picstart plus development programmer, or mplab icd 2 with a universal programmer adapter. the mplab icd 2 and mplab ice in-circuit emulators may also be used with the picdem 2 demonstration board to test firmware. a prototype area extends the circuitry for additional application components. some of the features include an rs-232 interface, a 2 x 16 lcd display, a piezo speaker, an on-board temperature sensor, four leds and sample pic18f452 and pic16f877 flash microcontrollers. 25.18 picdem 3 pic16c92x demonstration board the picdem 3 demonstration board supports the pic16c923 and pic16c924 in the plcc package. all the necessary hardware and software is included to run the demonstration programs. 25.19 picdem 4 8/14/18-pin demonstration board the picdem 4 can be used to demonstrate the capa- bilities of the 8, 14 and 18-pin pic16xxxx and pic18xxxx mcus, including the pic16f818/819, pic16f87/88, pic16f62xa and the pic18f1320 family of microcontrollers. picdem 4 is intended to showcase the many features of these low pin count parts, including lin and motor control using eccp. special provisions are made for low-power operation with the supercapacitor circuit and jumpers allow on- board hardware to be disabled to eliminate current draw in this mode. included on the demo board are pro- visions for crystal, rc or canned oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, db-9 rs-232 interface, icd connector for programming via icsp and development with mplab icd 2, 2 x 16 liquid crystal display, pcb footprints for h-bridge motor driver, lin transceiver and eeprom. also included are: header for expansion, eight leds, four potentiometers, three push buttons and a proto- typing area. included with the kit is a pic16f627a and a pic18f1320. tutorial firmware is included along with the user?s guide.
? 2004 microchip technology inc. preliminary ds39635a-page 341 pic18fx310/x410 25.20 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. a pro- grammed sample is included. the pro mate ii device programmer, or the picstart plus development pro- grammer, can be used to reprogram the device for user tailored application development. the picdem 17 demonstration board supports program download and execution from external on-board flash memory. a generous prototype area is available for user hardware expansion. 25.21 picdem 18r pic18c601/801 demonstration board the picdem 18r demonstration board serves to assist development of the pic18c601/801 family of microchip microcontrollers. it provides hardware implementation of both 8-bit multiplexed/demultiplexed and 16-bit memory modes. the board includes 2 mb external flash memory and 128 kb sram memory, as well as serial eeprom, allowing access to the wide range of memory types supported by the pic18c601/801. 25.22 picdem lin pic16c43x demonstration board the powerful lin hardware and software kit includes a series of boards and three picmicro microcontrollers. the small footprint pic16c432 and pic16c433 are used as slaves in the lin communication and feature on-board lin transceivers. a pic16f874 flash microcontroller serves as the master. all three micro- controllers are programmed with firmware to provide lin bus communication. 25.23 pickit tm 1 flash starter kit a complete ?development system in a box?, the pickit? flash starter kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin flash pic ? microcontrollers. powered via usb, the board operates under a simple windows gui. the pickit 1 starter kit includes the user?s guide (on cd rom), pickit 1 tutorial software and code for various applications. also included are mplab ? ide (integrated development environment) software, software and hardware ?tips 'n tricks for 8-pin flash pic ? microcontrollers? handbook and a usb interface cable. supports all current 8/14-pin flash pic microcontrollers, as well as many future planned devices. 25.24 picdem usb pic16c7x5 demonstration board the picdem usb demonstration board shows off the capabilities of the pic16c745 and pic16c765 usb microcontrollers. this board provides the basis for future usb products. 25.25 evaluation and programming tools in addition to the picdem series of circuits, microchip has a line of evaluation kits and demonstration software for these products. k ee l oq evaluation and programming tools for microchip?s hcs secure data products can developers kit for automotive network applications analog design boards and filter design software powersmart battery charging evaluation/ calibration kits irda ? development kit microid development and rflab tm development software seeval ? designer kit for memory evaluation and endurance calculations picdem msc demo boards for switching mode power supply, high-power ir driver, delta sigma adc and flow rate sensor check the microchip web page and the latest product selector guide for the complete list of demonstration and evaluation kits.
pic18fx310/x410 ds39635a-page 342 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 343 pic18f6310/6410/8310/8410 26.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr and ra4) .......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ......................................................................................... 0v to +13.25v voltage on ra4 with respect to vss ............................................................................................. .................. 0v to +8.5v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports ...................................................................................................................... .200 ma maximum current sourced by all ports ........................................................................................... .......................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v ol x i ol ) 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a ?low? level to the mclr /v pp pin, rather than pulling this pin directly to v ss . ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic18f6310/6410/8310/8410 ds39635a-page 344 preliminary ? 2004 microchip technology inc. figure 26-1: pic18f6310/6410/8310/8410 voltage-frequency graph (industrial) figure 26-2: pic18lf6310/6410/8310/8410 voltage-frequency graph (industrial) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 40 mhz 5.0v 3.5v 3.0v 2.5v pic18fx310/410 4.2v frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 40 mhz 5.0v 3.5v 3.0v 2.5v pic18lfx310/410 f max = (16.36 mhz/v) (v ddappmin ? 2.0v) + 4 mhz note: v ddappmin is the minimum voltage of the picmicro ? device in the application. 4 mhz 4.2v
? 2004 microchip technology inc. preliminary ds39635a-page 345 pic18f6310/6410/8310/8410 26.1 dc characteristics: supply voltage pic18f6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6310/6410/8310/8410 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min typ max units conditions v dd supply voltage d001 pic18lfx310/x410 2.0 ? 5.5 v hs, xt, rc and lp oscillator mode pic18fx310/x410 4.2 ? 5.5 v d002 v dr ram data retention voltage (1) 1.5 ? ? v d003 v por v dd start voltage to ensure internal power-on reset signal ? ? 0.7 v see section 4.3 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section 4.3 ?power-on reset (por)? for details v bor brown-out reset voltage d005 borv1:borv0 = 11 1.96 2.06 2.16 v borv1:borv0 = 10 2.64 2.78 2.92 v borv1:borv0 = 01 4.11 4.33 4.55 v borv1:borv0 = 00 4.41 4.64 4.87 v legend: shading of rows is to assist in readability of the table. note 1: this is the limit to which v dd can be lowered in sleep mode, or duri ng a device reset, without losing ram data.
pic18f6310/6410/8310/8410 ds39635a-page 346 preliminary ? 2004 microchip technology inc. 26.2 dc characteristics: power-down and supply current pic18f6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6310/6410/8310/8410 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions power-down current (i pd ) (1) pic18lfx310/x410 0.18 0.95 a -40c v dd = 2.0v, ( sleep mode) 0.19 1.0 a +25c 0.20 1.1 a +85c pic18lfx310/x410 0.27 0.95 a -40c v dd = 3.0v, ( sleep mode) 0.28 1.0 a +25c 0.30 1.1 a +85c all devices 0.42 1.9 a -40c v dd = 5.0v, ( sleep mode) 0.44 2.0 a +25c 0.47 2.1 a +85c legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
? 2004 microchip technology inc. preliminary ds39635a-page 347 pic18f6310/6410/8310/8410 supply current (i dd ) (2,3) pic18lfx310/x410 15.6 31.5 a -40c f osc = 31 khz ( rc_run mode, internal oscillator source) 14.8 30 a+25c v dd = 2.0v 14.1 28.5 a+85c pic18lfx310/x410 34 63 a -40c 32.4 57 a+25c v dd = 3.0v 30.7 60 a+85c all devices 83.2 168 a -40c 79.2 160 a+25c v dd = 5.0v 75.2 152 a+85c pic18lfx310/x410 339 630 a -40c f osc = 1 mhz ( rc_run mode, internal oscillator source) 323 600 a+25c v dd = 2.0v 306 570 a+85c pic18lfx310/x410 .55 1.3 ma -40c .52 1.2 ma +25c v dd = 3.0v .50 1.1 ma +85c all devices 1.2 2.3 ma -40c 1.1 2.2 ma +25c v dd = 5.0v 1.1 2.1 ma +85c pic18lfx310/x410 0.84 2.1 ma -40c f osc = 4 mhz ( rc_run mode, internal oscillator source) 0.80 2.0 ma +25c v dd = 2.0v 0.76 1.9 ma +85c pic18lfx310/x410 1.4 2.7 ma -40c 1.3 2.6 ma +25c v dd = 3.0v 1.3 2.5 ma +85c all devices 2.6 5.3 ma -40c 2.5 5.0 ma +25c v dd = 5.0v 2.4 4.8 ma +85c 26.2 dc characteristics: power-down and supply current pic18f6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) (continued) pic18lf6310/6410/8310/8410 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6310/6410/8310/8410 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
pic18f6310/6410/8310/8410 ds39635a-page 348 preliminary ? 2004 microchip technology inc. supply current (i dd ) (2,3) pic18lfx310/x410 3.3 6.5 a -40c f osc = 31 khz ( rc_idle mode, internal oscillator source) 3.1 6.2 a+25c v dd = 2.0v 3.0 5.9 a+85c pic18lfx310/x410 5.0 10.1 a -40c 4.8 9.6 a+25c v dd = 3.0v 4.6 9.1 a+85c all devices 10.3 15.8 a -40c 9.8 15.0 a+25c v dd = 5.0v 9.3 14.3 a+85c pic18lfx310/x410 183 368 a -40c f osc = 1 mhz ( rc_idle mode, internal oscillator source) 175 350 a+25c v dd = 2.0v 166 333 a+85c pic18lfx310/x410 280 473 a -40c 267 450 a+25c v dd = 3.0v 253 428 a+85c all devices 546 893 a -40c 520 850 a+25c v dd = 5.0v 494 808 a+85c pic18lfx310/x410 362 525 a -40c f osc = 4 mhz ( rc_idle mode, internal oscillator source) 344 500 a+25c v dd = 2.0v 327 475 a+85c pic18lfx310/x410 572 840 a -40c 544 800 a+25c v dd = 3.0v 517 760 a+85c all devices 1.2 1.6 ma -40c 1.1 1.5 ma +25c v dd = 5.0v 1.0 1.4 ma +85c 26.2 dc characteristics: power-down and supply current pic18f6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) (continued) pic18lf6310/6410/8310/8410 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6310/6410/8310/8410 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
? 2004 microchip technology inc. preliminary ds39635a-page 349 pic18f6310/6410/8310/8410 supply current (i dd ) (2,3) pic18lfx310/x410 271 420 a -40c f osc = 1 mh z ( pri_run , ec oscillator) 258 400 a+25c v dd = 2.0v 245 380 a+85c pic18lfx310/x410 502 735 a -40c 478 700 a+25c v dd = 3.0v 454 665 a+85c all devices 1.1 2.6 ma -40c 1.1 2.5 ma +25c v dd = 5.0v 1.0 2.4 ma +85c pic18lfx310/x410 0.78 1.6 ma -40c f osc = 4 mhz ( pri_run , ec oscillator) 0.74 1.5 ma +25c v dd = 2.0v 0.70 1.4 ma +85c pic18lfx310/x410 1.4 2.6 ma -40c 1.3 2.5 ma +25c v dd = 3.0v 1.2 2.4 ma +85c all devices 2.8 5.3 ma -40c 2.6 5.0 ma +25c v dd = 5.0v 2.5 4.8 ma +85c all devices 16.5 26.3 ma -40c f osc = 40 mh z ( pri_run , ec oscillator) 15.7 25.0 ma +25c v dd = 4.2v 14.9 23.8 ma +85c all devices 21.7 31.5 ma -40c 20.6 30.0 ma +25c v dd = 5.0v 19.6 28.5 ma +85c 26.2 dc characteristics: power-down and supply current pic18f6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) (continued) pic18lf6310/6410/8310/8410 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6310/6410/8310/8410 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
pic18f6310/6410/8310/8410 ds39635a-page 350 preliminary ? 2004 microchip technology inc. supply current (i dd ) (2,3) pic18lfx310/x410 68.2 126 a -40c f osc = 1 mhz ( pri_idle mode, ec oscillator) 65.0 120 a+25c v dd = 2.0v 61.7 114 a+85c pic18lfx310/x410 123 263 a -40c 117 250 a+25c v dd = 3.0v 111 238 a+85c all devices 241 473 a -40c 230 450 a+25c v dd = 5.0v 218 428 a+85c pic18lfx310/x410 268 473 a -40c f osc = 4 mhz ( pri_idle mode, ec oscillator) 255 450 a+25c v dd = 2.0v 242 428 a+85c pic18lfx310/x410 448 1000 a -40c 426 952 a+25c v dd = 3.0v 405 904 a+85c all devices 0.93 1.5 ma -40c 0.88 1.4 ma +25c v dd = 5.0v 0.84 1.3 ma +85c all devices 6.3 9.5 ma -40c f osc = 40 mhz ( pri_idle mode, ec oscillator) 6.0 9.0 ma +25c v dd = 4.2 v 5.7 8.6 ma +85c all devices 9.5 12.6 ma -40c 9.1 12.0 ma +25c v dd = 5.0v 8.6 11.4 ma +85c 26.2 dc characteristics: power-down and supply current pic18f6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) (continued) pic18lf6310/6410/8310/8410 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6310/6410/8310/8410 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
? 2004 microchip technology inc. preliminary ds39635a-page 351 pic18f6310/6410/8310/8410 supply current (i dd ) (2,3) pic18lfx310/x410 15.8 31.5 a -10c f osc = 32 khz (4) ( sec_run mode, timer1 as clock) 15.0 30.0 a+25c v dd = 2.0v 14.3 28.5 a+70c pic18lfx310/x410 33.4 73.5 a -10c 31.8 70.0 a+25c v dd = 3.0v 30.2 66.5 a+70c all devices 83.2 126 a -10c 79.2 120 a+25c v dd = 5.0v 75.2 114 a+70c pic18lfx310/x410 3.9 9.5 a -10c f osc = 32 khz (4) ( sec_idle mode, timer1 as clock) 3.7 9.0 a+25c v dd = 2.0v 3.5 8.6 a+70c pic18lfx310/x410 5.4 10.5 a -10c 5.1 10.0 a+25c v dd = 3.0v 4.8 9.5 a+70c all devices 9.4 16.8 a -10c 9.0 16.0 a+25c v dd = 5.0v 8.5 15.2 a+70c 26.2 dc characteristics: power-down and supply current pic18f6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) (continued) pic18lf6310/6410/8310/8410 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6310/6410/8310/8410 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
pic18f6310/6410/8310/8410 ds39635a-page 352 preliminary ? 2004 microchip technology inc. module differential currents ( ? i wdt , ? i bor , ? i lvd , ? i oscb , ? i ad ) d022 ( ? i wdt ) watchdog timer 1.3 3.8 a -40c 1.4 4.0 a+25c v dd = 2.0v 1.4 4.2 a+85c 1.9 4.8 a -40c 2.0 5.0 a+25c v dd = 3.0v 2.1 5.3 a+85c 5.2 9.5 a -40c 5.5 10.0 a+25c v dd = 5.0v 5.7 10.5 a+85c d022a ( ? i bor ) brown-out reset 32.2 52.3 a-40 c to +85 cv dd = 3.0v 35.6 63.0 a-40 c to +85 cv dd = 5.0v d022b ( ? i lvd ) low-voltage detect 19 31.5 a-40 c to +85 cv dd = 2.0v 21.7 31.5 a-40 c to +85 cv dd = 3.0v 24.3 36.8 a-40 c to +85 cv dd = 5.0v d025 ( ? i oscb ) timer1 oscillator 1.2 5.7 a-10 c 1.3 6.0 a+25 cv dd = 2.0v 32 khz on timer1 (4) 1.3 6.3 a+70 c 1.6 7.6 a-10 c 1.7 8.0 a+25 cv dd = 3.0v 32 khz on timer1 (4) 1.8 8.4 a+70 c 2.6 9.5 a-10 c 2.8 10.0 a+25 cv dd = 5.0v 32 khz on timer1 (4) 2.9 10.5 a+70 c d026 ( ? i ad ) a/d converter 1.0 3.0 a? v dd = 2.0v a/d on, not converting, 1.6 s t ad 6.4 s 1.0 4.0 a? v dd = 3.0v 1.0 10.0 a? v dd = 5.0v 26.2 dc characteristics: power-down and supply current pic18f6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) (continued) pic18lf6310/6410/8310/8410 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6310/6410/8310/8410 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
? 2004 microchip technology inc. preliminary ds39635a-page 353 pic18f6310/6410/8310/8410 26.3 dc characteristics: pic18f6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss 0.15 v dd vv dd < 4.5v d030a ? 0.8 v 4.5v v dd 5.5v d031 with schmitt trigger buffer rc3 and rc4 v ss v ss 0.2 v dd 0.3 v dd v v d032 mclr v ss 0.2 v dd v d032a osc1 and t1osi v ss 0.3 v dd v lp, xt, hs, hspll modes (1) d033 osc1 v ss 0.2 v dd vec mode (1) v ih input high voltage i/o ports: d040 with ttl buffer 0.25 v dd + 0.8v v dd vv dd < 4.5v d040a 2.0 v dd v4.5v v dd 5.5v d041 with schmitt trigger buffer rc3 and rc4 0.8 v dd 0.7 v dd v dd v dd v v d042 mclr 0.8 v dd v dd v d042a osc1 and t1osi 0.7 v dd v dd v lp, xt, hs, hspll modes (1) d043 osc1 0.8 v dd v dd vec mode (1) i il input leakage current (2,3) d060 i/o ports ? 1 av ss v pin v dd , pin at hi-impedance d061 mclr ? 5 av ss v pin v dd d063 osc1 ? 5 av ss v pin v dd i pu weak pull-up current d070 i purb portb weak pull-up current 50 400 av dd = 5v, v pin = v ss note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro ? device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: parameter is characterized but not tested.
pic18f6310/6410/8310/8410 ds39635a-page 354 preliminary ? 2004 microchip technology inc. v ol output low voltage d080 i/o ports ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d083 osc2/clko (rc, rcio, ec, ecio modes) ?0.6vi ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c v oh output high voltage (3) d090 i/o ports v dd ? 0.7 ? v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d092 osc2/clko (rc, rcio, ec, ecio modes) v dd ? 0.7 ? v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d150 v od open-drain high voltage ? 8.5 v ra4 pin capacitive loading specs on output pins d100 (4) c osc2 osc2 pin ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins and osc2 (in rc mode) ? 50 pf to meet the ac timing specifications d102 c b scl, sda ? 400 pf i 2 c specification 26.3 dc characteristics: pic18f6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min max units conditions note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro ? device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: parameter is characterized but not tested.
? 2004 microchip technology inc. preliminary ds39635a-page 355 pic18f6310/6410/8310/8410 table 26-1: memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. sym characteristic min typ? max units conditions program flash memory d110 v pp voltage on mclr /v pp pin 10.0 ? 12.0 v d113 i ddp supply current during programming ?? 1ma d130 e p cell endurance ? 1k ? e/w -40 c to +85 c d131 v pr v dd for read v min ?5.5vv min = minimum operating voltage d132 v ie v dd for block erase 4.5 ? 5.5 v using icsp port d132a v iw v dd for externally timed erase or write 4.5 ? 5.5 v using icsp port d132b v pew v dd for self-timed write v min ?5.5vv min = minimum operating voltage d133 t ie icsp? block erase cycle time ? 4 ? ms v dd > 4.5v d133a t iw icsp erase or write cycle time (externally timed) 2??msv dd > 4.5v d133a t iw self-timed write cycle time ? 2 ? ms d134 t retd characteristic retention 40 100 ? year provided no other specifications are violated ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic18f6310/6410/8310/8410 ds39635a-page 356 preliminary ? 2004 microchip technology inc. table 26-2: comparator specifications table 26-3: voltage reference specifications operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +85c, unless otherwise stated. param no. sym characteristics min typ max units comments d300 v ioff input offset voltage ? 5.0 10 mv d301 v icm input common mode voltage* 0 ? v dd ? 1.5 v d302 cmrr common mode rejection ratio* 55 ? ? db 300 t resp response time (1)* ? 150 400 ns pic18 f xxxx 300a ? 150 600 ns pic18 lf xxxx, v dd = 2.0v 301 t mc 2 ov comparator mode change to output valid* ?? 10 s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd . operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +85c, unless otherwise stated. param no. sym characteristics min typ max units comments d310 v res resolution v dd /24 ? v dd /32 lsb d311 vr aa absolute accuracy ? ? ? ? 1/4 1/2 lsb lsb low range (cvrr = 1 ) high range (cvrr = 0 ) d312 vr ur unit resistor value (r)* ? 2k ? ? 310 t set settling time (1) * ? ? 10 s * these parameters are characterized but not tested. note 1: settling time measured while cvrr = 1 and cvr3:cvr0 transitions from ? 0000 ? to ? 1111 ?.
? 2004 microchip technology inc. preliminary ds39635a-page 357 pic18f6310/6410/8310/8410 figure 26-3: high/low-voltage detect characteristics table 26-4: high/low-voltage detect characteristics v hlvd hlvdif v dd (hlvdif set by hardware) (hlvdif can be cleared in software) v hlvd for vdirmag = 1 : for vdirmag = 0 : v dd standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min typ? max units conditions d420 hlvd voltage on v dd transition lvv = 0000 1.80 1.86 1.91 v lvv = 0001 1.96 2.06 2.06 v lvv = 0010 2.16 2.27 2.38 v lvv = 0011 2.35 2.47 2.59 v lvv = 0100 2.43 2.56 2.69 v lvv = 0101 2.64 2.78 2.92 v lvv = 0110 2.75 2.89 3.03 v lvv = 0111 2.95 3.10 3.26 v lvv = 1000 3.24 3.41 3.58 v lvv = 1001 3.43 3.61 3.79 v lvv = 1010 3.53 3.72 3.91 v lvv = 1011 3.72 3.92 4.12 v lvv = 1100 3.92 4.13 4.34 v lvv = 1101 4.11 4.33 4.55 v lvv = 1110 4.41 4.64 4.87 v ? production tested at t amb = 25c. specifications over temperature limits ensured by characterization.
pic18f6310/6410/8310/8410 ds39635a-page 358 preliminary ? 2004 microchip technology inc. 26.4 ac (timing) characteristics 26.4.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t13cki mc mclr wr wr uppercase letters and their meanings: s f fall p period hhigh rrise i invalid (high-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition
? 2004 microchip technology inc. preliminary ds39635a-page 359 pic18f6310/6410/8310/8410 26.4.2 timing conditions the temperature and voltages specified in table 26-5 apply to all timing specifications unless otherwise noted. figure 26-4 specifies the load conditions for the timing specifications. table 26-5: temperature and voltage specifications ? ac figure 26-4: load conditions for devi ce timing specifications note: because of space limitations, the generic terms ?pic18fxxxx? and ?pic18lfxxxx? are used throughout this section to refer to the pic18f6310/6410/8310/8410 and pic18lf6310/6410/8310/8410 families of devices specifically and only those devices. ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial operating voltage v dd range as described in dc spec section 26.1 and section 26.3 . lf parts operate for industrial temperatures only. v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2/clko and including d and e outputs as ports load condition 1 load condition 2
pic18f6310/6410/8310/8410 ds39635a-page 360 preliminary ? 2004 microchip technology inc. 26.4.3 timing diagrams and specifications figure 26-5: external clock timing (all modes except pll) table 26-6: external clock timing requirements osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 param. no. symbol characteristic min max units conditions 1a f osc external clki frequency (1) dc 40 mhz ec, ecio oscillator frequency (1) dc 4 mhz rc oscillator 0.1 4 mhz xt oscillator 4 25 mhz hs oscillator 4 10 mhz hs + pll oscillator 5 200 khz lp oscillator mode 1t osc external clki period (1) 25 ? ns ec, ecio oscillator period (1) 250 ? ns rc oscillator 250 10,000 ns xt oscillator 25 100 250 250 ns ns hs oscillator hs + pll oscillator 25 ? s lp oscillator 2t cy instruction cycle time (1) 100 ? ns t cy = 4/f osc 3t os l, t os h external clock in (osc1) high or low time 30 ? ns xt oscillator 2.5 ? s lp oscillator 10 ? ns hs oscillator 4t os r, t os f external clock in (osc1) rise or fall time ? 20 ns xt oscillator ? 50 ns lp oscillator ? 7.5 ns hs oscillator note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period for all configurations except pll. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices.
? 2004 microchip technology inc. preliminary ds39635a-page 361 pic18f6310/6410/8310/8410 table 26-7: pll clock timing specifications (v dd = 4.2v to 5.5v) table 26-8: ac characteristics:internal rc accuracy pic18f6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) param no. sym characteristic min typ? max units conditions f10 f osc oscillator frequency range 4 ? 10 mhz hs mode only f11 f sys on-chip vco system frequency 16 ? 40 mhz hs mode only f12 t rc pll start-up time (lock time) ? ? 2 ms f13 ? clk clko stability (jitter) -2 ? +2 % ? data in ?typ? column is at 5v, 25 c, unless otherwise stated. these parameters are for design guidance only and are not tested. pic18lf6310/6410/8310/8410 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f6310/6410/8310/8410 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device min typ max units conditions intosc accuracy @ freq = 8 mhz, 4 mhz, 2 mhz, 1 mhz, 500 khz, 250 khz, 125 khz (1) pic18lf6310/6410/8310/8410 -2 +/-1 2 % +25c v dd = 2.7-3.3 v -5 ? 5 % -10c to +85c v dd = 2.7-3.3 v -10 +/-1 10 % -40c to +85c v dd = 2.7-3.3 v pic18f6310/6410/8310/8410 -2 +/-1 2 % +25c v dd = 4.5-5.5 v -5 ? 5 % -10c to +85c v dd = 4.5-5.5 v -10 +/-1 10 % -40c to +85c v dd = 4.5-5.5 v intrc accuracy @ freq = 31 khz (2) pic18lf6310/6410/8310/8410 26.562 ? 35.938 khz -40c to +85c v dd = 2.7-3.3 v pic18f6310/6410/8310/8410 26.562 ? 35.938 khz -40c to +85c v dd = 4.5-5.5 v intrc stability (3) f7 pic18lf6310/6410/8310/8410 tbd 1 tbd % +25c v dd = 2.0v f8 tbd 1 tbd % +25c v dd = 3.0v f9 all devices tbd 1 tbd % +25c v dd = 5.0v legend: tbd = to be determined. shading of rows is to assist in readability of the table. note 1: frequency calibrated at 25c. osctune register can be used to compensate for temperature drift. 2: intrc frequency after calibration. 3: change of intrc frequency as v dd changes.
pic18f6310/6410/8310/8410 ds39635a-page 362 preliminary ? 2004 microchip technology inc. figure 26-6: clko and i/o timing table 26-9: clko and i/o timing requirements note: refer to figure 26-4 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param no. symbol characteristic min typ max units conditions 10 t os h2 ck losc1 to clko ? 75 200 ns (note 1) 11 t os h2 ck hosc1 to clko ? 75 200 ns (note 1) 12 t ck r clko rise time ? 35 100 ns (note 1) 13 t ck f clko fall time ? 35 100 ns (note 1) 14 t ck l2 io vclko to port out valid ? ? 0.5 t cy + 20 ns (note 1) 15 t io v2 ck h port in valid before clko 0.25 t cy + 25 ? ? ns (note 1) 16 t ck h2 io i port in hold after clko 0??ns (note 1) 17 t os h2 io vosc1 (q1 cycle) to port out valid ? 50 150 ns 18 t os h2 io iosc1 (q2 cycle) to port input invalid (i/o in hold time) pic18 f xxxx 100 ? ? ns 18a pic18 lf xxxx 200 ? ? ns v dd = 2.0v 19 t io v2 os h port input valid to osc1 (i/o in setup time) 0 ? ? ns 20 t io r port output rise time pic18 f xxxx ? 10 25 ns 20a pic18 lf xxxx ? ? 60 ns v dd = 2.0v 21 t io f port output fall time pic18 f xxxx ? 10 25 ns 21a pic18 lf xxxx ? ? 60 ns v dd = 2.0v 22? t inp int pin high or low time t cy ??ns 23? t rbp rb7:rb4 change int high or low time t cy ??ns 24? t rcp rc7:rc4 change int high or low time 20 ns ? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode, where clko output is 4 x t osc .
? 2004 microchip technology inc. preliminary ds39635a-page 363 pic18f6310/6410/8310/8410 figure 26-7: program memo ry read timing diagram table 26-10: clko and i/o timing requirements param. no symbol characteristics min typ max units 150 tadv2all address out valid to ale (address setup time) 0.25 t cy ? 10 ? ? ns 151 tall2adl ale to address out invalid (address hold time) 5??ns 155 tall2oel ale to oe 10 0.125 t cy ?ns 160 tadz2oel ad high-z to oe (bus release to oe )0??ns 161 toeh2add oe to ad driven 0.125 t cy ? 5 ? ? ns 162 tadv2oeh ls data valid before oe (data setup time) 20 ? ? ns 163 toeh2adl oe to data in invalid (data hold time) 0 ? ? ns 164 talh2all ale pulse width ? t cy ?ns 165 toel2oeh oe pulse width 0.5 t cy ? 5 0.5 t cy ?ns 166 talh2alh ale to ale (cycle time) ? 0.25 t cy ?ns 167 tacc address valid to data valid 0.75 t cy ? 25 ? ? ns 168 toe oe to data valid ? 0.5 t cy ? 25 ns 169 tall2oeh ale to oe 0.625 t cy ? 10 ? 0.625 t cy + 10 ns 171 talh2csl chip enable active to ale 0.25 t cy ? 20 ? ? ns 171a tubl2oeh ad valid to chip enable active ? ? 10 ns q1 q2 q3 q4 q1 q2 osc1 ale oe address data from external 164 166 160 165 161 151 162 163 ad<15:0> 167 168 155 address address 150 ad<19:16> address 169 ba0 ce 171 171a operating conditions: 2.0v < v cc < 5.5v, -40c < t a < +125c unless otherwise stated.
pic18f6310/6410/8310/8410 ds39635a-page 364 preliminary ? 2004 microchip technology inc. figure 26-8: program memory write timing diagram table 26-11: program memory write timing requirements param. no symbol characteristics min typ max units 150 tadv2all address out valid to ale (address setup time) 0.25 t cy ? 10 ? ? ns 151 tall2adl ale to address out invalid (address hold time) 5 ? ? ns 153 twrh2adl wrn to data out invalid (data hold time) 5 ? ? ns 154 twrl wrn pulse width 0.5 t cy ? 5 0.5 t cy ?ns 156 tadv2wrh data valid before wrn (data setup time) 0.5 t cy ? 10 ? ? ns 157 tbsv2wrl byte select valid before wrn (byte select setup time) 0.25 t cy ??ns 157a twrh2bsi wrn to byte select invalid (byte select hold time) 0.125 t cy ? 5 ? ? ns 166 talh2alh ale to ale (cycle time) ? 0.25 t cy ?ns 171 talh2csl chip enable active to ale 0.25 t cy ? 20 ? ? ns 171a tubl2oeh ad valid to chip enable active ? ? 10 ns q1 q2 q3 q4 q1 q2 osc1 ale address data 156 150 151 153 ad<15:0> address wrh or wrl ub or lb 157 154 157a address ad<19:16> address ba0 166 ce 171 171a operating conditions: 2.0v < v cc < 5.5v, -40c < t a < +125c unless otherwise stated.
? 2004 microchip technology inc. preliminary ds39635a-page 365 pic18f6310/6410/8310/8410 figure 26-9: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 26-10: brown-out reset timing table 26-12: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements param. no. symbol characteristic min typ max units conditions 30 t mc lmclr pulse width (low) 2 ? ? s 31 t wdt watchdog timer time-out period (no postscaler) ?4.00tbd ms 32 t ost oscillation start-up timer period 1024 t osc ? 1024 t osc ?t osc = osc1 period 33 t pwrt power-up timer period ? 65.5 tbd ms 34 t ioz i/o high-impedance from mclr low or watchdog timer reset ?2? s 35 t bor brown-out reset pulse width 200 ? ? sv dd b vdd (see d005) 36 t ivrst time for internal reference voltage to become stable ?2050 s 37 t lvd low-voltage detect pulse width 200 ? ? sv dd v lvd 38 t csd cpu start-up time 5 ? 10 s 39 t iobst time for intrc block to stabilize ? 1 ? ms legend: tbd = to be determined v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 26-4 for load conditions. v dd bv dd 35 v bgap = 1.2v v irvst enable internal internal reference 36 reference voltage voltage stable
pic18f6310/6410/8310/8410 ds39635a-page 366 preliminary ? 2004 microchip technology inc. figure 26-11: timer0 and timer1 external clock timings table 26-13: timer0 and timer1 external clock requirements note: refer to figure 26-4 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t13cki tmr0 or tmr1 param no. symbol characteristic min max units conditions 40 t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 41 t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 42 t t 0p t0cki period no prescaler t cy + 10 ? ns with prescaler greater of: 20 ns or (t cy + 40)/n ?nsn = prescale value (1, 2, 4,..., 256) 45 t t 1h t13cki high time synchronous, no prescaler 0.5 t cy + 20 ? ns synchronous, with prescaler pic18 f xxxx 10 ? ns pic18 lf xxxx 25 ? ns v dd = 2.0v asynchronous pic18 f xxxx 30 ? ns pic18 lf xxxx 50 ? ns v dd = 2.0v 46 t t 1l t13cki low time synchronous, no prescaler 0.5 t cy + 5 ? ns synchronous, with prescaler pic18 f xxxx 10 ? ns pic18 lf xxxx 25 ? ns v dd = 2.0v asynchronous pic18 f xxxx 30 ? ns pic18 lf xxxx 50 ? ns v dd = 2.0v 47 t t 1p t13cki input period synchronous greater of: 20 ns or (t cy + 40)/n ?nsn = prescale value (1, 2, 4, 8) asynchronous 60 ? ns f t 1 t13cki oscillator input frequency range dc 50 khz 48 t cke 2 tmr i delay from external t13cki clock edge to timer increment 2 t osc 7 t osc ?
? 2004 microchip technology inc. preliminary ds39635a-page 367 pic18f6310/6410/8310/8410 figure 26-12: capture/compare/pwm timings (all ccp modules) table 26-14: capture/compare/pwm requirements (all ccp modules) note: refer to figure 26-4 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) param no. symbol characteristic min max units conditions 50 t cc l ccpx input low time no prescaler 0.5 t cy + 20 ? ns with prescaler pic18 f xxxx 10 ? ns pic18 lf xxxx 20 ? ns v dd = 2.0v 51 t cc h ccpx input high time no prescaler 0.5 t cy + 20 ? ns with prescaler pic18 f xxxx 10 ? ns pic18 lf xxxx 20 ? ns v dd = 2.0v 52 t cc p ccpx input period 3 t cy + 40 n ? ns n = prescale value (1, 4 or 16) 53 t cc r ccpx output fall time pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 54 t cc f ccpx output fall time pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v
pic18f6310/6410/8310/8410 ds39635a-page 368 preliminary ? 2004 microchip technology inc. figure 26-13: example spi ma ster mode timing (cke = 0 ) table 26-15: example spi mode requirements (master mode, cke = 0 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit 6 - - - - - - 1 msb in lsb in bit 6 - - - - 1 note: refer to figure 26-4 for load conditions. param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ss to sck or sck input t cy ?ns 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ns 75 t do r sdo data output rise time pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 76 t do f sdo data output fall time ? 25 ns 78 t sc r sck output rise time (master mode) pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 79 t sc f sck output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge pic18 f xxxx ? 50 ns pic18 lf xxxx ? 100 ns v dd = 2.0v note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used.
? 2004 microchip technology inc. preliminary ds39635a-page 369 pic18f6310/6410/8310/8410 figure 26-14: example spi ma ster mode timing (cke = 1 ) table 26-16: example spi mode requirements (master mode, cke = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit 6 - - - - - - 1 lsb in bit 6 - - - - 1 lsb note: refer to figure 26-4 for load conditions. param. no. symbol characteristic min max units conditions 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ns 75 t do r sdo data output rise time pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 76 t do f sdo data output fall time ? 25 ns 78 t sc r sck output rise time (master mode) pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 79 t sc f sck output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge pic18 f xxxx ? 50 ns pic18 lf xxxx ? 100 ns v dd = 2.0v 81 t do v2 sc h, t do v2 sc l sdo data output setup to sck edge t cy ?ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used.
pic18f6310/6410/8310/8410 ds39635a-page 370 preliminary ? 2004 microchip technology inc. figure 26-15: example spi slave mode timing (cke = 0 ) table 26-17: example spi mode requirements (slave mode timing, cke = 0 ) param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ss to sck or sck input t cy ?ns 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ns 75 t do r sdo data output rise time pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 76 t do f sdo data output fall time ? 25 ns 77 t ss h2 do zss to sdo output high-impedance 10 50 ns 78 t sc r sck output rise time (master mode) pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 79 t sc f sck output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge pic18 f xxxx ? 50 ns pic18 lf xxxx ? 100 ns v dd = 2.0v 83 t sc h2 ss h, t sc l2 ss h ss after sck edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit 6 - - - - - - 1 msb in bit 6 - - - - 1 lsb in 83 note: refer to figure 26-4 for load conditions.
? 2004 microchip technology inc. preliminary ds39635a-page 371 pic18f6310/6410/8310/8410 figure 26-16: example spi slave mode timing (cke = 1 ) table 26-18: example spi slave mode requirements (cke = 1 ) param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ss to sck or sck input t cy ?ns 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ns 75 t do r sdo data output rise time pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 76 t do f sdo data output fall time ? 25 ns 77 t ss h2 do zss to sdo output high-impedance 10 50 ns 78 t sc r sck output rise time (master mode) pic18 f xxxx ? 25 ns pic18 lf xxxx ? 45 ns v dd = 2.0v 79 t sc f sck output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge pic18 f xxxx ? 50 ns pic18 lf xxxx ? 100 ns v dd = 2.0v 82 t ss l2 do v sdo data output valid after ss edge pic18 f xxxx ? 50 ns pic18 lf xxxx ? 100 ns v dd = 2.0v 83 t sc h2 ss h, t sc l2 ss h ss after sck edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit 6 - - - - - - 1 lsb 77 msb in bit 6 - - - - 1 lsb in 80 83 note: refer to figure 26-4 for load conditions.
pic18f6310/6410/8310/8410 ds39635a-page 372 preliminary ? 2004 microchip technology inc. figure 26-17: i 2 c bus start/stop bits timing table 26-19: i 2 c bus start/stop bits requirements (slave mode) figure 26-18: i 2 c bus data timing note: refer to figure 26-4 for load conditions. 91 92 93 scl sda start condition stop condition 90 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? 92 t su : sto stop condition 100 khz mode 4700 ? ns setup time 400 khz mode 600 ? 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? note: refer to figure 26-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
? 2004 microchip technology inc. preliminary ds39635a-page 373 pic18f6310/6410/8310/8410 table 26-20: i 2 c bus data requirements (slave mode) param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? s pic18fxxxx must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s pic18fxxxx must operate at a minimum of 10 mhz ssp module 1.5 t cy ? 101 t low clock low time 100 khz mode 4.7 ? s pic18fxxxx must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s pic18fxxxx must operate at a minimum of 10 mhz ssp module 1.5 t cy ? 102 t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110 t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s d102 c b bus capacitive loading ? 400 pf note 1: as a transmitter, the device must provi de this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but the requirement, t su : dat 250 ns, must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released.
pic18f6310/6410/8310/8410 ds39635a-page 374 preliminary ? 2004 microchip technology inc. figure 26-19: master ssp i 2 c bus start/stop bits timing waveforms table 26-21: master ssp i 2 c bus start/stop bits requirements figure 26-20: master ssp i 2 c bus data timing note: refer to figure 26-4 for load conditions. 91 93 scl sda start condition stop condition 90 92 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns only relevant for repeated start condition setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 91 t hd : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns after this period, the first clock pulse is generated hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 92 t su : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 93 t hd : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? note 1: maximum pin capacitance = 10 pf for all i 2 c pins. note: refer to figure 26-4 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
? 2004 microchip technology inc. preliminary ds39635a-page 375 pic18f6310/6410/8310/8410 table 26-22: master ssp i 2 c bus data requirements param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 102 t r sda and scl rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 300 ns 103 t f sda and scl fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 100 ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ? ms after this period, the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ms 1 mhz mode (1) tbd ? ns 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 1 mhz mode (1) tbd ? ns 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 109 t aa output valid from clock 100 khz mode ? 3500 ns 400 khz mode ? 1000 ns 1 mhz mode (1) ??ns 110 t buf bus free time 100 khz mode 4.7 ? ms time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ms 1 mhz mode (1) tbd ? ms d102 c b bus capacitive loading ? 400 pf legend: tbd = to be determined note 1: maximum pin capacitance = 10 pf for all i 2 c pins. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but parameter #107 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 khz mode,) before the scl line is released.
pic18f6310/6410/8310/8410 ds39635a-page 376 preliminary ? 2004 microchip technology inc. figure 26-21: usart synchronous transmission (master/slave) timing table 26-23: usart synchronous transmission requirements figure 26-22: usart synchronous receive (master/slave) timing table 26-24: usart synchronous receive requirements 121 121 120 122 rc6/tx1/ck1 rc7/rx1/dt1 pin pin note: refer to figure 26-4 for load conditions. param no. symbol characteristic min max units conditions 120 t ck h2 dt v sync xmit (master and slave) clock high to data out valid pic18 f xxxx ? 40 ns pic18 lf xxxx ? 100 ns v dd = 2.0v 121 t ckrf clock out rise time and fall time (master mode) pic18 f xxxx ? 20 ns pic18 lf xxxx ? 50 ns v dd = 2.0v 122 t dtrf data out rise time and fall time pic18 f xxxx ? 20 ns pic18 lf xxxx ? 50 ns v dd = 2.0v 125 126 rc6/tx1/ck1 rc7/rx1/dt1 pin pin note: refer to figure 26-4 for load conditions. param. no. symbol characteristic min max units conditions 125 t dt v2 ckl sync rcv (master and slave) data hold before ck (dt hold time) 10 ? ns 126 t ck l2 dtl data hold after ck (dt hold time) 15 ? ns
? 2004 microchip technology inc. preliminary ds39635a-page 377 pic18f6310/6410/8310/8410 table 26-25: a/d converter characteristics: pic18f6310/6410/8310/8410 (industrial) pic18lf6310/6410/8310/8410 (industrial) param no. symbol characteristic min typ max units conditions a01 n r resolution ? ? 10 bit ? v ref 3.0v a03 e il integral linearity error ? ? <1 lsb ? v ref 3.0v a04 e dl differential linearity error ? ? <1 lsb ? v ref 3.0v a06 e off offset error ? ? <1 lsb ? v ref 3.0v a07 e gn gain error ? ? <1 lsb ? v ref 3.0v a10 ? monotonicity guaranteed (1) ? a20 ? v ref reference voltage range (v refh ? v refl ) 3?av dd ? av ss v for 10-bit resolution a21 v refh reference voltage high av ss + 3.0v ? av dd + 0.3v v for 10-bit resolution a22 v refl reference voltage low av ss ? 0.3v ? av dd ? 3.0v v for 10-bit resolution a25 v ain analog input voltage v refl ?v refh v a28 av dd analog supply voltage v dd ? 0.3 ? v dd + 0.3 v a29 av ss analog supply voltage v ss ? 0.3 ? v ss + 0.3 v a30 z ain recommended impedance of analog voltage source ??2.5k ? a40 i ad a/d conversion current (v dd ) pic18 f xxxx ? 180 ? a average current consumption when a/d is on (note 2) pic18 lf xxxx ? 90 ? av dd = 2.0v; average current consumption when a/d is on (note 2) a50 i ref v ref input current (note 3) ? ? ? ? 5 150 a a during v ain acquisition. during a/d conversion cycle. note 1: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 2: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 3: v refh current is from ra3/an3/v ref + pin or av dd , whichever is selected as the v refh source. v refl current is from ra2/an2/v ref - pin or av ss , whichever is selected as the v refl source.
pic18f6310/6410/8310/8410 ds39635a-page 378 preliminary ? 2004 microchip technology inc. figure 26-23: a/d conversion timing table 26-26: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 987 21 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . t cy param no. symbol characteristic min max units conditions 130 t ad a/d clock period pic18 f xxxx 0.7 25.0 (1) st osc based, v ref 3.0v pic18 lf xxxx tbd tbd sv dd = 2.0v; t osc based, v ref full range pic18 f xxxx tbd tbd s a/d rc mode pic18 lf xxxx tbd tbd sv dd = 2.0v; a/d rc mode 131 t cnv conversion time (not including acquisition time) (note 2) 11 12 t ad 132 t acq acquisition time (note 3) 1.4 tbd ? ? s s -40 c to +85 c 0 c to +85 c 135 t swc switching time from convert sample ? (note 4) tbd t dis discharge time 0.2 ? s legend: tbd = to be determined note 1: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. 2: adres register may be read on the following t cy cycle. 3: the time for the holding capacitor to acquire the ?new? input voltage when the voltage changes full scale after the conversion (av dd to av ss or av ss to av dd ). the source impedance ( r s ) on the input channels is 50 ? . 4: on the following cycle of the device clock.
? 2004 microchip technology inc. preliminary ds39635a-page 379 pic18f6310/6410/8310/8410 27.0 dc and ac characteristics graphs and tables graphs and tables are not available at this time.
pic18f6310/6410/8310/8410 ds39635a-page 380 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 381 pic18f6310/6410/8310/8410 28.0 packaging information 28.1 package marking information 64-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example pic18f6410 -i/pt 0410017 80-lead tqfp xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic18f8410-e /pt 0410017 legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard picmicro device marking consists of microchip part number, year code, week code and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price.
pic18f6310/6410/8310/8410 ds39635a-page 382 preliminary ? 2004 microchip technology inc. 28.2 package details the following sections give the technical details of the packages. 64-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 0.27 0.22 0.17 .011 .009 .007 b lead width 0.23 0.18 0.13 .009 .007 .005 c lead thickness 16 16 n1 pins per side 10.10 10.00 9.90 .398 .394 .390 d1 molded package length 10.10 10.00 9.90 .398 .394 .390 e1 molded package width 12.25 12.00 11.75 .482 .472 .463 d overall length 12.25 12.00 11.75 .482 .472 .463 e overall width 7 3.5 0 7 3.5 0 foot angle 0.75 0.60 0.45 .030 .024 .018 l foot length 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.05 1.00 0.95 .041 .039 .037 a2 molded package thickness 1.20 1.10 1.00 .047 .043 .039 a overall height 0.50 .020 p pitch 64 64 n number of pins max nom min max nom min dimension limits millimeters* inches units c 2 1 n d d1 b p #leads=n1 e1 e a2 a1 a l ch x 45 (f) footprint (reference) (f) .039 1.00 pin 1 corner chamfer ch .025 .035 .045 0.64 0.89 1.14 shall not exceed .010" (0.254mm) per side. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions notes: jedec equivalent: ms-026 drawing no. c04-085 *controlling parameter
? 2004 microchip technology inc. preliminary ds39635a-page 383 pic18f6310/6410/8310/8410 80-lead plastic thin quad flatpack (pt) 12x12x1 mm body, 1.0/0.10 mm lead form (tqfp) 1.10 1.00 .043 .039 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) e e1 #leads=n1 p b d1 d n 1 2 c l a a1 a2 units inches millimeters* dimension limits min nom max min nom max number of pins n 80 80 pitch p .020 0.50 overall height a .047 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .541 .551 .561 13.75 14.00 14.25 overall length d .541 .551 .561 13.75 14.00 14.25 molded package width e1 .463 .472 .482 11.75 12.00 12.25 molded package length d1 .463 .472 .482 11.75 12.00 12.25 pins per side n1 20 20 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .007 .009 .011 0.17 0.22 0.27 mold draft angle top 5 10 15 5 10 15 mold draft angle bottom 5 10 15 5 10 15 ch x 45 shall not exceed .010" (0.254mm) per side. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions notes: jedec equivalent: ms-026 drawing no. c04-092 *controlling parameter
pic18f6310/6410/8310/8410 ds39635a-page 384 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 385 pic18f6310/6410/8310/8410 appendix a: revision history revision a (june 2004) original data sheet for pic18f6310/6410/8310/8410 devices. appendix b: device differences the differences between the devices listed in this data sheet are shown in table b-1. table b-1: device differences features pic18f6310 pic18f6410 pic18f8310 pic18f8410 program memory (bytes) 8k 16k 8k 16k program memory (instructions) 4096 8192 4096 8192 external memory interface no no yes yes i/o ports ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g, h, j ports a, b, c, d, e, f, g, h, j packages 64-pin tqfp 64-pin tqfp 80-pin tqfp 80-pin tqfp
pic18f6310/6410/8310/8410 ds39635a-page 386 preliminary ? 2004 microchip technology inc. appendix c: conversion considerations this appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. typically, these changes are due to the differences in the process technology used. an example of this type of conversion is from a pic16c74a to a pic16c74b. not applicable appendix d: migration from baseline to enhanced devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to an enhanced mcu device (i.e., pic18fxxx). the following are the list of modifications over the pic16c5x microcontroller family: not currently available
? 2004 microchip technology inc. preliminary ds39635a-page 387 pic18f6310/6410/8310/8410 appendix e: migration from mid-range to enhanced devices a detailed discussion of the differences between the mid-range mcu devices (i.e., pic16cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an716, ?migrating designs from pic16c74a/74b to pic18c442? . the changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. this application note is available as literature number ds00716. appendix f: migration from high-end to enhanced devices a detailed discussion of the migration pathway and differences between the high-end mcu devices (i.e., pic17cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an726, ?pic17cxxx to pic18cxxx migration? . this application note is available as literature number ds00726.
pic18f6310/6410/8310/8410 ds39635a-page 388 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds39635a-page 389 pic18f6310/6410/8310/8410 index a a/d ................................................................................... 245 a/d converter interrupt, configuring ....................... 249 acquisition requirements ........................................ 250 adcon0 register .................................................... 245 adcon1 register .................................................... 245 adcon2 register .................................................... 245 adresh register ............................................ 245, 248 adresl register .................................................... 245 analog port pins ...................................................... 140 analog port pins, configuring .................................. 252 associated registers ............................................... 254 automatic acquisition time ...................................... 251 calculating the minimum required acquisition time .............................................. 250 configuring the module ............................................ 249 conversion clock (t ad ) ........................................... 251 conversion status (go/done bit) .......................... 248 conversions ............................................................. 253 converter characteristics ........................................ 377 discharge ................................................................. 253 operation in power managed modes ...................... 252 special event trigger (ccp) .................................... 254 use of the ccp2 trigger .......................................... 254 absolute maximum ratings ............................................. 343 ac (timing) characteristics ............................................. 358 load conditions for device timing specifications ....................................... 359 parameter symbology ............................................. 358 temperature and voltage specific ations ................. 359 timing conditions .................................................... 359 access bank ...................................................................... 71 ackstat ........................................................................ 199 ackstat status flag ..................................................... 199 adcon0 register ............................................................ 245 go/done bit ........................................................... 248 adcon1 register ............................................................ 245 adcon2 register ............................................................ 245 addfsr .......................................................................... 330 addlw ............................................................................ 293 addressable universal synchronous asynchronous receiver transmitter (ausart). see ausart. addulnk ........................................................................ 330 addwf ............................................................................ 293 addwfc ......................................................................... 294 adresh register ............................................................ 245 adresl register .................................................... 245, 248 analog-to-digital converter. see a/d. andlw ............................................................................ 294 andwf ............................................................................ 295 assembler mpasm assembler .................................................. 337 ausart asynchronous mode ................................................ 236 associated registers, receive ........................ 239 associated registers, transmit ....................... 237 receiver ........................................................... 238 setting up 9-bit mode with address detect ...... 238 transmitter ....................................................... 236 baud rate generator (brg) ................................... 234 associated registers ....................................... 234 baud rate error, calculating ........................... 234 baud rates, asynchronous modes ................. 235 high baud rate select (brgh bit) ................. 234 operation in power managed modes .............. 234 sampling ......................................................... 234 synchronous master mode ...................................... 240 associated registers, receive ........................ 242 associated registers, transmit ....................... 241 reception ........................................................ 242 transmission ................................................... 240 synchronous slave mode ........................................ 243 associated registers, receive ........................ 244 associated registers, transmit ....................... 243 reception ........................................................ 244 transmission ................................................... 243 auto-wake-up on sync break character ......................... 222 b bank select register (bsr) .............................................. 69 baud rate generator ...................................................... 195 bc .................................................................................... 295 bcf ................................................................................. 296 bf .................................................................................... 199 bf status flag ................................................................. 199 block diagrams 16-bit byte select mode ............................................ 93 16-bit byte write mode .............................................. 91 16-bit word write mode ............................................ 92 8-bit multiplexed mode .............................................. 96 a/d ........................................................................... 248 analog input model .................................................. 249 ausart receive .................................................... 238 ausart transmit ................................................... 236 baud rate generator .............................................. 195 capture mode operation ......................................... 161 comparator i/o operating modes ....................................... 256 comparator analog input model .............................. 259 comparator output .................................................. 258 comparator voltage reference ............................... 262 compare mode operation ....................................... 163 device clock .............................................................. 34 eusart receive .................................................... 220 eusart transmit ................................................... 218 external power-on reset circuit (slow v dd power-up) ........................................ 51 fail-safe clock monitor ........................................... 282 generic i/o port operation ...................................... 117 high/low-voltage detect with external input .................................................. 266 interrupt logic .......................................................... 102 mssp (i 2 c master mode) ........................................ 193 mssp (i 2 c mode) .................................................... 178 mssp (spi mode) ................................................... 169 on-chip reset circuit ................................................ 49 pic18f6310/6410 ..................................................... 10 pic18f8310/8410 ..................................................... 11 pll (hs mode) .......................................................... 31 portd and porte (parallel slave port) ............... 140 pwm operation (simplified) .................................... 165
pic18f6310/6410/8310/8410 ds39635a-page 390 preliminary ? 2004 microchip technology inc. reads from program memory .................................... 86 single comparator ................................................... 257 table read and table write operations ................... 85 timer0 in 16-bit mode .............................................. 144 timer0 in 8-bit mode ................................................ 144 timer1 ...................................................................... 148 timer1 (16-bit read/write mode) ............................ 148 timer2 ...................................................................... 154 timer3 ...................................................................... 156 timer3 (16-bit read/write mode) ............................ 156 voltage reference output buffer example ........................................................... 263 watchdog timer ....................................................... 279 bn .................................................................................... 296 bnc .................................................................................. 297 bnn .................................................................................. 297 bnov ............................................................................... 298 bnz .................................................................................. 298 bor. see brown-out reset. bov .................................................................................. 301 bra .................................................................................. 299 break character (12-bit) transmit and receive ............................................................. 224 brg. see baud rate generator. brown-out reset (bor) ............................................. 52, 271 detecting .................................................................... 52 disabling in sleep mode ............................................ 52 software enabled ....................................................... 52 bsf .................................................................................. 299 btfsc ............................................................................. 300 btfss .............................................................................. 300 btg .................................................................................. 301 bz ..................................................................................... 302 c c compilers mplab c17 ............................................................. 338 mplab c18 ............................................................. 338 mplab c30 ............................................................. 338 call ................................................................................ 302 capture (ccp module) ..................................................... 161 associated registers ............................................... 164 ccp pin configuration ............................................. 161 ccpr2h:ccpr2l registers ................................... 161 software interrupt .................................................... 162 timer1/timer3 mode selection ................................ 161 capture/compare/pwm (ccp) ........................................ 159 capture mode. see capture. ccp mode and timer resources ............................ 160 ccprxh register .................................................... 160 ccprxl register ..................................................... 160 compare mode. see compare. interconnect configurations ..................................... 160 module configuration ............................................... 160 clock sources .................................................................... 34 selecting the 31 khz source ...................................... 35 selection using osccon register ........................... 35 clrf ................................................................................ 303 clrwdt .......................................................................... 303 code examples 16 x 16 signed multiply routine .............................. 100 16 x 16 unsigned multiply routine .......................... 100 8 x 8 signed multiply routine .................................... 99 8 x 8 unsigned multiply routine ................................ 99 changing between capture prescalers ................... 162 computed goto using an offset value ................... 66 fast register stack ................................................... 66 how to clear ram (bank 1) using indirect addressing ............................................ 78 implementing a real-time clock using a timer1 interrupt service .................................. 151 initializing porta .................................................... 117 initializing portb .................................................... 120 initializing portc ................................................... 123 initializing portd ................................................... 126 initializing porte .................................................... 129 initializing portf .................................................... 132 initializing portg ................................................... 134 initializing porth ................................................... 136 initializing portj .................................................... 138 loading the sspbuf (sspsr) register ................. 172 reading a flash program memory word .................. 87 saving status, wreg and bsr registers in ram .................................... 116 code protection ............................................................... 271 comf .............................................................................. 304 comparator ...................................................................... 255 analog input connection considerations ................ 259 associated registers ............................................... 259 configuration ........................................................... 256 effects of a reset .................................................... 258 interrupts ................................................................. 258 operation ................................................................. 257 operation during sleep ........................................... 258 outputs .................................................................... 257 reference ................................................................ 257 external signal ................................................ 257 internal signal .................................................. 257 response time ........................................................ 257 comparator specifications ............................................... 356 comparator voltage reference ....................................... 261 accuracy and error .................................................. 262 associated registers ............................................... 263 configuring .............................................................. 261 connection considerations ...................................... 262 effects of a reset .................................................... 262 operation during sleep ........................................... 262 compare (ccp module) .................................................. 162 associated registers ............................................... 164 ccp pin configuration ............................................. 162 ccpr2 register ...................................................... 162 software interrupt mode .......................................... 162 special event trigger .............................. 157, 162, 254 timer1/timer3 mode selection ................................ 162 computed goto ............................................................... 66 configuration bits ............................................................ 271 configuration register protection .................................... 284 context saving during interrupts ..................................... 116
? 2004 microchip technology inc. preliminary ds39635a-page 391 pic18f6310/6410/8310/8410 conversion considerations .............................................. 386 cpfseq .......................................................................... 304 cpfsgt .......................................................................... 305 cpfslt ........................................................................... 305 crystal oscillator/ceramic resonator ................................ 29 d data addressing modes ..................................................... 78 comparing addressing modes with the extended instruction set enabled ..................... 82 direct .......................................................................... 78 indexed literal offset ................................................. 81 indirect ....................................................................... 78 inherent and literal .................................................... 78 data memory ..................................................................... 69 access bank .............................................................. 71 and the extended instruction set ............................... 81 bank select register (bsr) ....................................... 69 general purpose registers ........................................ 71 map for pic18f6310/6410/8310/8410 devices .............................................................. 70 special function registers ........................................ 72 daw ................................................................................. 306 dc and ac characteristics graphs and tables .......................... 379 dc characteristics ........................................................... 353 power-down and supply current ............................ 346 supply voltage ......................................................... 345 dcfsnz .......................................................................... 307 decf ............................................................................... 306 decfsz ........................................................................... 307 demonstration boards picdem 1 ................................................................ 340 picdem 17 .............................................................. 341 picdem 18r ........................................................... 341 picdem 2 plus ........................................................ 340 picdem 3 ................................................................ 340 picdem 4 ................................................................ 340 picdem lin ............................................................ 341 picdem usb ........................................................... 341 picdem.net internet/ethernet ................................. 340 development support ...................................................... 337 device differences ........................................................... 385 device overview .................................................................. 7 features (table) ............................................................ 9 new core features ...................................................... 7 direct addressing ............................................................... 79 e effect on standard pic instructions ................................. 334 effects of power managed modes on various clock sources ............................................................ 37 electrical characteristics .................................................. 343 enhanced universal synchronous asynchronous receiver transmitter (eusart). see eusart. equations a/d acquisition time ................................................ 250 a/d minimum charging time ................................... 250 errata ................................................................................... 5 eusart asynchronous mode ................................................ 218 12-bit break transmit and receive ................. 224 associated registers, receive ........................ 221 associated registers, transmit ....................... 219 auto-wake-up on sync break ......................... 222 receiver .......................................................... 220 setting up 9-bit mode with address detect ........................................ 220 transmitter ...................................................... 218 baud rate generator (brg) ................................... 213 associated registers ....................................... 213 auto-baud rate detect .................................... 216 baud rate error, calculating ........................... 213 baud rates, asynchronous modes ................. 214 high baud rate select (brgh bit) ................. 213 operation in power managed modes .............. 213 sampling ......................................................... 213 synchronous master mode ...................................... 225 associated registers, receive ........................ 227 associated registers, transmit ....................... 226 reception ........................................................ 227 transmission ................................................... 225 synchronous slave mode ........................................ 228 associated registers, receive ........................ 229 associated registers, transmit ....................... 228 reception ........................................................ 229 transmission ................................................... 228 evaluation and programming tools ................................. 341 extended instruction set addfsr .................................................................. 330 addulnk ............................................................... 330 and using mplab tools ......................................... 336 callw .................................................................... 331 considerations for use ............................................ 334 movsf .................................................................... 331 movss .................................................................... 332 pushl ..................................................................... 332 subfsr .................................................................. 333 subulnk ................................................................ 333 external clock input ........................................................... 30 external memory interface ................................................. 89 16-bit byte select mode ............................................ 93 16-bit byte write mode .............................................. 91 16-bit mode ............................................................... 91 16-bit mode timing ................................................... 94 16-bit word write mode ............................................ 92 8-bit mode ................................................................. 96 8-bit mode timing ..................................................... 97 and the program memory modes .............................. 90 pic18f8310/8410 external bus, i/o port functions .............................................. 90 f fail-safe clock monitor ........................................... 271, 282 interrupts in power managed modes ....................... 283 por or wake from sleep ........................................ 283 wdt during oscillator failure ................................. 282 fast register stack ........................................................... 66
pic18f6310/6410/8310/8410 ds39635a-page 392 preliminary ? 2004 microchip technology inc. firmware instructions ....................................................... 287 flash program memory associated registers ................................................. 88 operation during code-protect ................................. 88 reading ...................................................................... 86 fscm. see fail-safe clock monitor. g goto ............................................................................... 308 h hardware multiplier ............................................................ 99 introduction ................................................................ 99 operation ................................................................... 99 performance comparison .......................................... 99 high/low-voltage detect ................................................. 265 associated registers ............................................... 269 characteristics ......................................................... 357 current consumption ............................................... 267 effects of a reset ..................................................... 269 operation ................................................................. 266 during sleep .................................................... 269 start-up time ................................................... 267 setup ........................................................................ 267 typical application ................................................... 268 hlvd. see high/low-voltage detect. i i/o ports ........................................................................... 117 i 2 c mode (mssp) acknowledge sequence timing ............................... 202 associated registers ............................................... 208 baud rate generator ............................................... 195 bus collision during a repeated start condition .................. 206 during a start condition ................................... 204 during a stop condition ................................... 207 clock arbitration ....................................................... 196 clock stretching ....................................................... 188 10-bit slave receive mode (sen = 1) ................................................. 188 7-bit slave receive mode (sen = 1) ................................................. 188 effect of a reset ...................................................... 203 general call address support ................................. 192 i 2 c clock rate w/brg ............................................. 195 master mode ............................................................ 193 operation ......................................................... 194 reception ......................................................... 199 repeated start condition timing ..................... 198 start condition ................................................. 197 transmission .................................................... 199 transmit sequence .......................................... 194 multi-master communication, bus collision and arbitration .................................................. 203 multi-master mode ................................................... 203 operation ................................................................. 182 read/write bit information (r/w bit) ............... 182, 183 registers .................................................................. 178 serial clock (rc3/sck/scl) ................................... 183 slave mode .............................................................. 182 addressing ....................................................... 182 reception ......................................................... 183 sleep operation ....................................................... 203 stop condition timing .............................................. 202 transmission ............................................................ 183 id locations ............................................................. 271, 285 idle modes pri_idle ................................................................... 44 incf ................................................................................ 308 incfsz ............................................................................ 309 in-circuit debugger .......................................................... 285 in-circuit serial programming (icsp) ...................... 271, 285 indexed literal offset addressing and standard pic18 instructions ............................. 334 indexed literal offset mode ....................................... 81, 334 bsr ........................................................................... 83 effect on standard pic18 instructions ....................... 81 mapping the access bank ......................................... 83 indirect addressing ............................................................ 79 infsnz ............................................................................ 309 initialization conditions for all registers ...................... 57?60 instruction cycle ................................................................ 67 clocking scheme ....................................................... 67 instruction flow/pipelining ................................................. 67 instruction set .................................................................. 287 addlw .................................................................... 293 addwf .................................................................... 293 addwf (indexed literal offset mode) .................... 335 addwfc ................................................................. 294 andlw .................................................................... 294 andwf .................................................................... 295 bc ............................................................................ 295 bcf ......................................................................... 296 bn ............................................................................ 296 bnc ......................................................................... 297 bnn ......................................................................... 297 bnov ...................................................................... 298 bnz ......................................................................... 298 bov ......................................................................... 301 bra ......................................................................... 299 bsf .......................................................................... 299 bsf (indexed literal offset mode) .......................... 335 btfsc ..................................................................... 300 btfss ..................................................................... 300 btg ......................................................................... 301 bz ............................................................................ 302 call ........................................................................ 302 clrf ....................................................................... 303 clrwdt ................................................................. 303 comf ...................................................................... 304 cpfseq .................................................................. 304 cpfsgt .................................................................. 305 cpfslt ................................................................... 305 daw ........................................................................ 306 dcfsnz .................................................................. 307 decf ....................................................................... 306 decfsz .................................................................. 307 extended instructions .............................................. 329 syntax .............................................................. 329 general format ........................................................ 289 goto ...................................................................... 308 incf ........................................................................ 308 incfsz .................................................................... 309 infsnz .................................................................... 309 iorlw ..................................................................... 310 iorwf ..................................................................... 310 lfsr ....................................................................... 311 movf ...................................................................... 311 movff .................................................................... 312 movlb .................................................................... 312 movlw ................................................................... 313
? 2004 microchip technology inc. preliminary ds39635a-page 393 pic18f6310/6410/8310/8410 movwf ................................................................... 313 mullw .................................................................... 314 mulwf .................................................................... 314 negf ....................................................................... 315 nop ......................................................................... 315 opcode field descriptions ....................................... 288 pop ......................................................................... 316 push ....................................................................... 316 rcall ..................................................................... 317 reset ..................................................................... 317 retfie .................................................................... 318 retlw .................................................................... 318 return .................................................................. 319 rlcf ........................................................................ 319 rlncf ..................................................................... 320 rrcf ....................................................................... 320 rrncf ................................ .................................... 321 setf ........................................................................ 321 setf (indexed literal offset mode) ........................ 335 sleep ..................................................................... 322 subfwb .................................................................. 322 sublw .................................................................... 323 subwf .................................................................... 323 subwfb .................................................................. 324 swapf .................................................................... 324 tblrd ..................................................................... 325 tblwt ..................................................................... 326 tstfsz ................................................................... 327 xorlw .................................................................... 327 xorwf .................................................................... 328 summary table ........................................................ 290 intcon register rbif bit .................................................................... 120 intcon registers ........................................................... 103 inter-integrated circuit. see i 2 c. internal oscillator block ..................................................... 32 adjustment ................................................................. 32 intio modes .............................................................. 32 intosc frequency drift ............................................ 32 intosc output frequency ........................................ 32 osctune register ................................................... 32 internal rc oscillator use with wdt .......................................................... 279 interrupt sources ............................................................. 271 a/d conversion complete ....................................... 249 interrupt-on-change (rb7:rb4) .............................. 120 intn pin ................................................................... 116 portb, interrupt-on-change .................................. 116 tmr0 ....................................................................... 116 tmr0 overflow ........................................................ 145 tmr1 overflow ........................................................ 147 tmr2 to pr2 match (pwm) .................................... 165 tmr3 overflow ................................................ 155, 157 interrupts .......................................................................... 101 interrupts, flag bits interrupt-on-change (rb7:rb4) flag (rbif bit) ................................................. 120 intosc, intrc. see internal oscillator block. iorlw ............................................................................. 310 iorwf ............................................................................. 310 ipr registers ................................................................... 112 l lfsr ................................................................................ 311 m master clear (mclr ) ......................................................... 51 master synchronous serial port (mssp). see mssp. memory organization ........................................................ 61 data memory ............................................................. 69 program memory ....................................................... 61 memory programming requirements .............................. 355 migration from baseline to enhanced devices ................ 386 migration from high-end to enhanced devices ............... 387 migration from mid-range to enhanced devices ............ 387 movf .............................................................................. 311 movff ............................................................................ 312 movlb ............................................................................ 312 movlw ........................................................................... 313 movss ............................................................................ 332 movwf ........................................................................... 313 mplab asm30 assembler, linker, librarian .................. 338 mplab icd 2 in-circuit debugger .................................. 339 mplab ice 2000 high-performance universal in-circuit emulator ................................................... 339 mplab ice 4000 high-performance universal in-circuit emulator ................................................... 339 mplab integrated development environment software ............................................. 337 mplab pm3 device programmer ................................... 339 mplink object linker/mplib object librarian ............... 338 mssp ack pulse ....................................................... 182, 183 control registers (general) ..................................... 169 i 2 c mode. see i 2 c mode. module overview ..................................................... 169 spi master/slave connection .................................. 173 spi mode. see spi mode. sspbuf .................................................................. 174 sspsr .................................................................... 174 mullw ............................................................................ 314 mulwf ............................................................................ 314 n negf ............................................................................... 315 nop ................................................................................. 315 o option_reg register psa bit .................................................................... 145 t0cs bit .................................................................. 144 t0ps2:t0ps0 bits ................................................... 145 t0se bit .................................................................. 144 oscillator configuration ................ ..................................... 29 ec .............................................................................. 29 ecio .......................................................................... 29 hs .............................................................................. 29 hspll ....................................................................... 29 internal oscillator block ............................................. 32 intio1 ....................................................................... 29 intio2 ....................................................................... 29 lp .............................................................................. 29 rc ............................................................................. 29 rcio .......................................................................... 29 xt .............................................................................. 29 oscillator selection .......................................................... 271
pic18f6310/6410/8310/8410 ds39635a-page 394 preliminary ? 2004 microchip technology inc. oscillator start-up timer (ost) ........................... 37, 53, 271 oscillator switching ............................................................ 34 oscillator transitions .......................................................... 35 oscillator, timer1 ..................................................... 147, 157 oscillator, timer3 ............................................................. 155 p packaging ........................................................................ 381 details ...................................................................... 382 marking .................................................................... 381 parallel slave port (psp) ................................................. 140 associated registers ............................................... 142 re0/rd pin .............................................................. 140 re1/wr pin ............................................................. 140 re2/cs pin .............................................................. 140 select (pspmode bit) ............................................ 140 pickit 1 flash starter kit .................................................. 341 picstart plus development programmer .................... 340 pie registers ................................................................... 109 pin functions av dd .......................................................................... 28 av dd .......................................................................... 19 av ss .......................................................................... 28 av ss .......................................................................... 19 osc1/clki/ra7 .................................................. 12, 20 osc2/clko/ra6 ................................................ 12, 20 ra0/an0 .............................................................. 13, 21 ra1/an1 .............................................................. 13, 21 ra2/an2/v ref - .................................................... 13, 21 ra3/an3/v ref + ................................................... 13, 21 ra4/t0cki ........................................................... 13, 21 ra5/an4/hlvdin ................................................ 13, 21 rb0/int0 ............................................................. 14, 22 rb1/int1 ............................................................. 14, 22 rb2/int2 ............................................................. 14, 22 rb3/int3 ................................................................... 14 rb3/int3/ccp2 ......................................................... 22 rb4/kbi0 ............................................................. 14, 22 rb5/kbi1 ............................................................. 14, 22 rb6/kbi2/pgc .................................................... 14, 22 rb7/kbi3/pgd .................................................... 14, 22 rc0/t1oso/t13cki ........................................... 15, 23 rc1/t1osi/ccp2 ................................................ 15, 23 rc2/ccp1 ........................................................... 15, 23 rc3/sck/scl ..................................................... 15, 23 rc4/sdi/sda ...................................................... 15, 23 rc5/sdo ............................................................. 15, 23 rc6/tx1/ck1 ...................................................... 15, 23 rc7/rx1/dt1 ...................................................... 15, 23 rd0/ad0/psp0 .......................................................... 24 rd0/psp0 .................................................................. 16 rd1/ad1/psp1 .......................................................... 24 rd1/psp1 .................................................................. 16 rd2/ad2/psp2 .......................................................... 24 rd2/psp2 .................................................................. 16 rd3/ad3/psp3 .......................................................... 24 rd3/psp3 .................................................................. 16 rd4/ad4/psp4 .......................................................... 24 rd4/psp4 .................................................................. 16 rd5/ad5/psp5 .......................................................... 24 rd5/psp5 .................................................................. 16 rd6/ad6/psp6 .......................................................... 24 rd6/psp6 .................................................................. 16 rd7/ad7/psp7 .......................................................... 24 rd7/psp7 .................................................................. 16 re0/ad8/rd .............................................................. 25 re0/rd ..................................................................... 17 re1/ad9/wr ............................................................. 25 re1/wr ..................................................................... 17 re2/ad10/cs ............................................................ 25 re2/cs ...................................................................... 17 re3 ............................................................................ 17 re3/ad11 .................................................................. 25 re4 ............................................................................ 17 re4/ad12 .................................................................. 25 re5 ............................................................................ 17 re5/ad13 .................................................................. 25 re6 ............................................................................ 17 re6/ad14 .................................................................. 25 re7/ccp2 ................................................................. 17 re7/ccp2/ad15 ....................................................... 25 rf0/an5 .............................................................. 18, 26 rf1/an6/c2out ................................................. 18, 26 rf2/an7/c1out ................................................. 18, 26 rf3/an8 .............................................................. 18, 26 rf4/an9 .............................................................. 18, 26 rf5/an10/cv ref ................................................ 18, 26 rf6/an11 ............................................................ 18, 26 rf7/ss ................................................................ 18, 26 rg0/ccp3 ........................................................... 19, 27 rg1/tx2/ck2 ...................................................... 19, 27 rg2/rx2/dt2 ...................................................... 19, 27 rg3 ..................................................................... 19, 27 rg4 ..................................................................... 19, 27 rg5 ..................................................................... 19, 27 rg5/mclr /v pp ................................................... 12, 20 rh0/ad16 ................................................................. 27 rh1/ad17 ................................................................. 27 rh2/ad18 ................................................................. 27 rh3/ad19 ................................................................. 27 rh4 ........................................................................... 27 rh5 ........................................................................... 27 rh6 ........................................................................... 27 rh7 ........................................................................... 27 rj0/ale .................................................................... 28 rj1/oe ...................................................................... 28 rj2/wrl ................................................................... 28 rj3/wrh ................................................................... 28 rj4/ba0 .................................................................... 28 rj5/ce ...................................................................... 28 rj6/lb ....................................................................... 28 rj7/ub ...................................................................... 28 v dd ............................................................................ 28 v dd ............................................................................ 19 v ss ............................................................................ 28 v ss ............................................................................ 19 pinout i/o descriptions pic18f6310/6410 ..................................................... 12 pic18f8310/8410 ..................................................... 20 pir registers ................................................................... 106 pll .................................................................................... 31 hspll oscillator mode ............................................. 31 use with intosc ................................................ 31, 32 pll lock time-out ............................................................. 53 pop ................................................................................. 316 por. see power-on reset. porta associated registers ............................................... 119 functions ................................................................. 118 lata register ......................................................... 117 porta register ...................................................... 117 trisa register ........................................................ 117
2004 microchip technology inc. preliminary ds39635a-page 395 pic18f6310/6410/8310/8410 portb associated registers ............................................... 122 functions ................................................................. 121 latb register .......................................................... 120 portb register ...................................................... 120 rb7:rb4 interrupt-on-change flag (rbif bit) ......................................................... 120 trisb register ........................................................ 120 portc associated registers ............................................... 125 functions ................................................................. 124 latc register ......................................................... 123 portc register ...................................................... 123 rc3/sck/scl pin ................................................... 183 trisc register ........................................................ 123 portd ............................................................................ 140 associated registers ............................................... 128 functions ................................................................. 127 latd register ......................................................... 126 portd register ...................................................... 126 trisd register ........................................................ 126 porte analog port pins ...................................................... 140 associated registers ............................................... 131 functions ................................................................. 130 late register .......................................................... 129 porte register ...................................................... 129 psp mode select (pspmode bit) .......................... 140 re0/rd pin .............................................................. 140 re1/wr pin ............................................................. 140 re2/cs pin .............................................................. 140 trise register ........................................................ 129 portf associated registers ............................................... 133 functions ................................................................. 133 latf register .......................................................... 132 portf register ...................................................... 132 trisf register ........................................................ 132 portg associated registers ............................................... 135 functions ................................................................. 135 latg register ......................................................... 134 portg register ...................................................... 134 trisg register ........................................................ 134 porth associated registers ............................................... 137 functions ................................................................. 137 lath register ......................................................... 136 porth register ...................................................... 136 trish register ........................................................ 136 portj associated registers ............................................... 139 functions ................................................................. 139 latj register .......................................................... 138 portj register ....................................................... 138 trisj register ......................................................... 138 postscaler, wdt assignment (psa bit) .............................................. 145 rate select (t0ps2:t0ps0 bits) ............................. 145 switching between timer0 and wdt ...................... 145 power managed modes ..................................................... 39 and multiple sleep commands .................................. 40 clock sources ........................................................... 39 clock transitions, status indicators .......................... 40 entering ..................................................................... 39 exiting idle and sleep modes .................................... 46 by interrupt ........................................................ 46 by reset ............................................................ 46 by wdt time-out .............................................. 46 without an oscillator start-up delay ................. 46 idle modes ................................................................. 43 run modes ................................................................ 40 selecting .................................................................... 39 sleep mode ............................................................... 43 summary (table) ........................................................ 39 power-on reset (por) .............................................. 51, 271 oscillator start-up timer (ost) ................................. 53 power-up timer (pwrt) ................................... 53, 271 time-out sequence ................................................... 53 power-up delays ............................................................... 37 power-up timer (pwrt) ............................................. 37, 53 prescaler, capture ........................................................... 162 prescaler, timer0 ............................................................ 145 assignment (psa bit) .............................................. 145 rate select (t0ps2:t0ps0 bits) ............................. 145 switching between timer0 and wdt ...................... 145 prescaler, tmr2 .............................................................. 166 pro mate ii universal device programmer .................. 339 program counter ............................................................... 64 pcl, pch and pcu registers .................................. 64 pclath and pclatu registers .............................. 64 program memory ............................................................... 85 and the extended instruction set .............................. 81 code protection ....................................................... 284 control registers ....................................................... 86 tablat (table latch) register ........................ 86 tblptr (table pointer) register ...................... 86 erasing external memory (pic18f8x10) .................. 87 instructions ................................................................ 68 two-word instructions ....................................... 68 interrupt vector .......................................................... 61 look-up tables .......................................................... 66 map and stack (diagram) .......................................... 61 memory access for pic18f8310/8410 modes .......... 63 memory maps for pic18fx310/x410 modes ............ 63 pic18f8310/8410 memory modes ............................ 62 reset vector .............................................................. 61 table reads and table writes .................................. 85 writing and erasing on-chip program memory (icsp mode) ........................................ 87 writing to unexpected termination ................................... 87 write verify ........................................................ 87 writing to memory space (pic18f8x10) .................. 87 program memory modes extended microcontroller ........................................... 90 microcontroller ........................................................... 90 microprocessor .......................................................... 90 microprocessor with boot block ................................ 90 program verification and code protection ...................... 284 associated registers ............................................... 284 programming, device instructions ................................... 287 psp. see parallel slave port. pulse-width modulation. see pwm (ccp module). push ............................................................................... 316
pic18f6310/6410/8310/8410 ds39635a-page 396 preliminary ? 2004 microchip technology inc. push and pop instructions .............................................. 65 pushl ............................................................................. 332 pwm (ccp module) associated registers ............................................... 167 duty cycle ................................................................ 166 example frequencies/resolutions .......................... 166 period ....................................................................... 165 setup for pwm operation ........................................ 166 tmr2 to pr2 match ................................................ 165 q q clock ............................................................................ 166 r ram. see data memory. rc oscillator ...................................................................... 31 rcio oscillator mode ................................................ 31 rcall .............................................................................. 317 rcon register bit status during initialization .................................... 56 register file ....................................................................... 71 register file summary ................................................. 73?76 registers adcon0 (a/d control 0) ......................................... 245 adcon1 (a/d control 1) ......................................... 246 adcon2 (a/d control 2) ......................................... 247 baudcon1 (baud rate control 1) ......................... 212 ccpxcon (capture/compare/pwm control ? ccp1, ccp2, ccp3) ....................................... 159 cmcon (comparator control) ................................ 255 config1h (configuration 1 high) .......................... 272 config2h (configuration 2 high) .......................... 274 config2l (configuration 2 low) ............................ 273 config3h (configuration 3 high) .......................... 275 config3l (configuration 3 low) ............................ 275 config3l (configuration byte 3 low) ..................... 62 config4l (configuration 4 low) ............................ 276 config5l (configuration 5 low) ............................ 276 config7l (configuration 7 low) ............................ 277 cvrcon (comparator voltage reference control) ........................................... 261 device id register 1 ................................................ 278 device id register 2 ................................................ 278 hlvdcon (hlvd control) ...................................... 265 intcon (interrupt control) ...................................... 103 intcon2 (interrupt control 2) ................................. 104 intcon3 (interrupt control 3) ................................. 105 ipr1 (peripheral interrupt priority 1) ........................ 112 ipr2 (peripheral interrupt priority 2) ........................ 113 ipr3 (peripheral interrupt priority 3) ........................ 114 memcon (memory control) ...................................... 89 osccon (oscillator control) .................................... 36 osctune (oscillator tuning) ................................... 33 pie1 (peripheral interrupt enable 1) ........................ 109 pie2 (peripheral interrupt enable 2) ........................ 110 pie3 (peripheral interrupt enable 3) ........................ 111 pir1 (peripheral interrupt request (flag) 1) ........................................................... 106 pir2 (peripheral interrupt request (flag) 2) ........................................................... 107 pir3 (peripheral interrupt request (flag) 3) ........................................................... 108 pspcon (parallel slave port control) .................... 141 rcon (reset control) ....................................... 50, 115 rcsta1 (eusart receive status and control) ..................................................... 211 rcsta2 (ausart receive status and control) ..................................................... 233 sspcon1 (mssp control 1, i 2 c mode) ................. 180 sspcon1 (mssp control 1, spi mode) ................. 171 sspcon2 (mssp control 2, i 2 c mode) ................. 181 sspstat (mssp status, i 2 c mode) ...................... 179 sspstat (mssp status, spi mode) ...................... 170 status ........................................................................ 77 stkptr (stack pointer) ............................................ 65 t0con (timer0 control) ......................................... 143 t1con (timer1 control) ......................................... 147 t2con (timer 2 control) ........................................ 153 t3con (timer3 control) ......................................... 155 txsta1 (eusart transmit status and control) ..................................................... 210 txsta2 (ausart transmit status and control) ..................................................... 232 wdtcon (watchdog timer control) ...................... 280 reset ................................................................................. 49 mclr reset, normal operation ................................ 49 mclr reset, power managed modes ...................... 49 power-on reset (por) .............................................. 49 programmable brown-out reset (bor) .................... 49 reset instruction ..................................................... 49 stack full reset ......................................................... 49 stack underflow reset .............................................. 49 watchdog timer (wdt) reset .................................. 49 resets .............................................................................. 271 retfie ............................................................................ 318 retlw ............................................................................ 318 return .......................................................................... 319 return address stack ........................................................ 64 return stack pointer (stkptr) ........................................ 65 revision history ............................................................... 385 rlcf ............................................................................... 319 rlncf ............................................................................. 320 rrcf ............................................................................... 320 rrncf ........................ .................................................... 321 run modes pri_run ................................................................... 40 rc_run .................................................................... 42 sec_run .................................................................. 40 s sck ................................................................................. 169 sdi ................................................................................... 169 sdo ................................................................................. 169 serial clock, sck ............................................................ 169 serial data in (sdi) .......................................................... 169 serial data out (sdo) ..................................................... 169 serial peripheral interface. see spi mode. setf ................................................................................ 321 slave select (ss ) ............................................................. 169 sleep ............................................................................. 322 sleep mode osc1 and osc2 pin states ...................................... 37 software simulator (mplab sim) ................................... 338 software simulator (mplab sim30) ............................... 338 special event trigger. see compare (ccp module). special features of the cpu ........................................... 271 special function registers ................................................ 72 map ............................................................................ 72 spi mode (mssp) associated registers ............................................... 177 bus mode compatibility ........................................... 177 effects of a reset .................................................... 177
? 2004 microchip technology inc. preliminary ds39635a-page 397 pic18f6310/6410/8310/8410 enabling spi i/o ...................................................... 173 master mode ............................................................ 174 master/slave connection ......................................... 173 operation ................................................................. 172 serial clock .............................................................. 169 serial data in ........................................................... 169 serial data out ........................................................ 169 slave mode .............................................................. 175 slave select ............................................................. 169 slave select synchronization .................................. 175 sleep operation ....................................................... 177 spi clock ................................................................. 174 typical connection .................................................. 173 ss .................................................................................... 169 sspov ............................................................................. 199 sspov status flag ......................................................... 199 sspstat register r/w bit ............................................................. 182, 183 stack full/underflow resets .............................................. 66 standard instructions ....................................................... 287 subfsr .......................................................................... 333 subfwb .......................................................................... 322 sublw ............................................................................ 323 subulnk ........................................................................ 333 subwf ............................................................................ 323 subwfb .......................................................................... 324 swapf ............................................................................ 324 t table pointer operations (table) ........................................ 86 table reads/table writes ................................................. 66 tblrd ............................................................................. 325 tblwt ............................................................................. 326 time-out in various situations (table) ................................ 53 timer0 .............................................................................. 143 16-bit mode timer reads and writes ...................... 144 associated registers ............................................... 145 clock source edge select (t0se bit) ...................... 144 clock source select (t0cs bit) ............................... 144 operation ................................................................. 144 overflow interrupt .................................................... 145 prescaler. see prescaler, timer0. timer1 .............................................................................. 147 16-bit read/write mode ........................................... 149 associated registers ............................................... 151 interrupt .................................................................... 150 low-power option ................................................... 149 operation ................................................................. 148 oscillator .......................................................... 147, 149 oscillator layout considerations ............................. 150 overflow interrupt .................................................... 147 resetting, using a special event trigger output (ccp) ....................................... 150 tmr1h register ...................................................... 147 tmr1l register ....................................................... 147 use as a real-time clock ....................................... 150 using as a clock source .......................................... 149 timer2 .............................................................................. 153 associated registers ............................................... 154 interrupt .................................................................... 154 operation ................................................................. 153 output ...................................................................... 154 pr2 register ............................................................ 165 tmr2 to pr2 match interrupt .................................. 165 timer3 ............................................................................. 155 16-bit read/write mode .......................................... 157 associated registers ............................................... 157 operation ................................................................. 156 oscillator .......................................................... 155, 157 overflow interrupt ............................................ 155, 157 special event trigger (ccp) ................................... 157 tmr3h register ...................................................... 155 tmr3l register ...................................................... 155 timing diagrams a/d conversion ....................................................... 378 acknowledge sequence .......................................... 202 asynchronous reception ................................. 221, 239 asynchronous transmission ........................... 219, 237 asynchronous transmission (back to back) ......................................... 219, 237 automatic baud rate calculation ............................ 217 auto-wake-up bit (wue) during normal operation ............................................ 223 auto-wake-up bit (wue) during sleep ................... 223 baud rate generator with clock arbitration ............ 196 brg overflow sequence ........................................ 217 brg reset due to sda arbitration during start condition ..................................... 205 brown-out reset (bor) ........................................... 365 bus collision during a repeated start condition (case 1) .................................. 206 bus collision during a repeated start condition (case 2) .................................. 206 bus collision during a start condition (scl = 0) ......................................... 205 bus collision during a start condition (sda only) ...................................... 204 bus collision during a stop condition (case 1) ........................................... 207 bus collision during a stop condition (case 2) ........................................... 207 bus collision for transmit and acknowledge ................................................... 203 capture/compare/pwm (all ccp modules) ........................................... 367 clko and i/o .......................................................... 362 clock synchronization ............................................. 189 clock/instruction cycle .............................................. 67 example spi master mode (cke = 0) ..................... 368 example spi master mode (cke = 1) ..................... 369 example spi slave mode (cke = 0) ....................... 370 example spi slave mode (cke = 1) ....................... 371 external clock (all modes except pll) ................... 360 external memory bus for sleep (16-bit microprocessor mode) ........................... 95 external memory bus for sleep (8-bit microprocessor mode) ............................. 98 external memory bus for tblrd (16-bit extended microcontroller mode) ............ 94 external memory bus for tblrd (16-bit microprocessor mode) ........................... 94 external memory bus for tblrd (8-bit extended microcontroller mode) .............. 97 external memory bus for tblrd (8-bit microprocessor mode) ............................. 97 fail-safe clock monitor ........................................... 283 high/low-voltage detect (vdirmag = 1) ............... 268 high/low-voltage detect characteristics ................ 357
pic18f6310/6410/8310/8410 ds39635a-page 398 preliminary ? 2004 microchip technology inc. high/low-voltage detect operation (vdirmag = 0) ................................................ 267 i 2 c bus data ............................................................ 372 i 2 c bus start/stop bits ............................................. 372 i 2 c master mode (7 or 10-bit transmission) ........................................ 200 i 2 c master mode (7-bit reception) .......................... 201 i 2 c master mode first start bit ................................ 197 i 2 c slave mode (10-bit recepti on, sen = 0) .......... 186 i 2 c slave mode (10-bit recepti on, sen = 1) .......... 191 i 2 c slave mode (10-bit transmission) ..................... 187 i 2 c slave mode (7-bit reception, sen = 0) ............. 184 i 2 c slave mode (7-bit reception, sen = 1) ............ 190 i 2 c slave mode (7-bit transmission) ....................... 185 i 2 c slave mode general call address sequence (7 or 10-bit address mode) ............. 192 i 2 c stop condition receive or transmit mode ................................................. 202 master ssp i 2 c bus data ........................................ 374 master ssp i 2 c bus start/stop bits ........................ 374 parallel slave port (psp) read ............................... 142 parallel slave port (psp) write ............................... 141 program memory read ............................................ 363 program memory write ............................................ 364 pwm output ............................................................ 165 repeat start condition ............................................. 198 reset, watchdog timer (wdt), oscillator start-up timer (ost) and power-up timer (pwrt) ................................. 365 send break character sequence ............................ 224 slave synchronization ............................................. 175 slow rise time (mclr tied to v dd , v dd rise > t pwrt ) ............................................ 55 spi mode (master mode) ......................................... 174 spi mode (slave mode, cke = 0) ........................... 176 spi mode (slave mode, cke = 1) ........................... 176 synchronous reception (master mode, sren) .............................. 227, 242 synchronous transmission .............................. 225, 240 synchronous transmission (through txen) ....................................... 226, 241 time-out sequence on por w/pll enabled (mclr tied to v dd ) ........................................... 55 time-out sequence on power-up (mclr not tied to v dd , case 1) ....................... 54 time-out sequence on power-up (mclr not tied to v dd , case 2) ....................... 54 time-out sequence on power-up (mclr tied to v dd , v dd rise t pwrt ) .............. 54 timer0 and timer1 external clock .......................... 366 transition for entry to pri_idle mode ...................... 44 transition for entry to sec_run mode .................... 41 transition for entry to sleep mode ............................ 43 transition for two-speed start-up (intosc to hspll) ......................................... 281 transition for wake from idle to run mode ............... 44 transition for wake from sleep (hspll) ................... 43 transition from rc_run mode to pri_run mode ................................................. 42 transition from sec_run mode to pri_run mode (hspll) ......... ......................... 41 transition to rc_run mode ..................................... 42 usart synchronous receive (master/slave) .................................................. 376 usart synchronous transmission (master/slave) ................................................. 376 timing diagrams and specifications a/d conversion requirements ................................ 378 ac characteristics internal rc accuracy ....................................... 361 capture/compare/pwm requirements (all ccp modules) ........................................... 367 clko and i/o requirements ........................... 362, 363 example spi mode requirements (master mode, cke = 0) .................................. 368 example spi mode requirements (master mode, cke = 1) .................................. 369 example spi mode requirements (slave mode, cke = 0) .................................... 370 example spi slave mode requirements (cke = 1) ......................................................... 371 external clock requirements .................................. 360 i 2 c bus data requirements (slave mode) .............. 373 i 2 c bus start/stop bits requirements (slave mode) ................................................... 372 master ssp i 2 c bus data requirements ................ 375 master ssp i 2 c bus start/stop bits requirements .................................................. 374 pll clock ................................................................ 361 program memory write requirements .................... 364 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements ...................... 365 timer0 and timer1 external clock requirements ........................................ 366 usart synchronous receive requirements .................................................. 376 usart synchronous transmission requirements .................................................. 376 top-of-stack access .......................................................... 64 trise register pspmode bit .......................................................... 140 tstfsz ........................................................................... 327 two-speed start-up ................................................. 271, 281 two-word instructions example cases .......................................................... 68 txsta1 register brgh bit ................................................................. 213 txsta2 register brgh bit ................................................................. 234 v voltage reference specifications .................................... 356 w watchdog timer (wdt) ........................................... 271, 279 associated registers ............................................... 280 control register ....................................................... 279 during oscillator failure .......................................... 282 programming considerations .................................. 279 wcol ...................................................... 197, 198, 199, 202 wcol status flag ................................... 197, 198, 199, 202 www, on-line support ................... ................................... 5 x xorlw ............................................................................ 327 xorwf ........................................................................... 328
? 2004 microchip technology inc. preliminary ds39635a-page 399 pic18f6310/6410/8310/8410 on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user?s guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip?s development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada and 1-480-792-7302 for the rest of the world. 042003
pic18f6310/6410/8310/8410 ds39635a-page 400 preliminary ? 2004 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39635a pic18f6310/6410/8310/8410 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2004 microchip technology inc. preliminary ds39635a-page 401 pic18f6310/6410/8310/8410 pic18f6310/6410/8310/8410 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device pic18f6310/6410/8310/8410 (1) , pic18f6310/6410/8310/8410t (2) ; v dd range 4.2v to 5.5v pic18lf6310/6410/8310/8410 (1) , pic18lf6310/6410/8310/8410t (2) ; v dd range 2.0v to 5.5v temperature range i = -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package pt = tqfp (thin quad flatpack) pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18lf6410-i/pt 301 = industrial temp., tqfp package, extended v dd limits, qtp pattern #301. b) pic18f8410-i/pt = industrial temp., tqfp package, normal v dd limits. c) pic18f8410-e/pt = extended temp., tqfp package, normal v dd limits. note 1: f = standard voltage range lf = wide voltage range 2: t = in tape and reel
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